GTLP2T152 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – 2-Bit LVTTL/GTLP Transceiver

June 2001
Revised February 2002
GTLP2T152
2-Bit LVTTL/GTLP Transceiver
General Description
The GTLP2T152 is a 2-bit transceiver that provides LVTTL-
to-GTLP signal level translation. Data directional control is
handled with a transmit/receive pin. High-speed backplane
operation is a direct result of GTLP’s reduced output swing
(<1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus-settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage and temperature compensated. GTLP’s I/O
structure is similar to GTL and BTL but offers different out-
put levels and receiver threshold. Typical GTLP output volt-
age levels are: V_OL = 0.5V, V_OH = 1.5V, and V_REF = 1V.
Features
s Bidirectional interface between GTLP and LVTTL logic
levels
s Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s V_REF pin provides external supply reference voltage for
receiver threshold adjustibility
s Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s TTL compatible driver and control inputs
s Designed using Fairchild advanced BiCMOS technology
s Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s Power up/down and power off high impedance for live
insertion
s Open drain on GTLP to support wired-or connection
s Flow through pinout optimizes PCB layout
s A Port source/sink −24mA/+24mA
s B Port sink +50mA
Ordering Code:
Order Number
GTLP2T152M
GTLP2T152MX
GTLP2T152K8X
Package Number Package Description
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
MAB08A
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
(Preliminary) [TAPE and REEL]
Pin Descriptions
Connection Diagrams
Pin Names
Description
T/R
LVTTL Direction Control
(Receive Direction is Active LOW)
V_CC, GND, V_REF Device Supplies
A_n
A Port LVTTL Input/Output
B_n
B Port GTLP Input/Output
US8
SOIC
© 2002 Fairchild Semiconductor Corporation DS500486
www.fairchildsemi.com