FSTU162450 Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – Configurable 4-Bit to 20-Bit Bus Switch with .2V Undershoot Protection and 25Ω Series Resistors in Outputs (Preliminary)

Preliminary
February 2001
Revised August 2001
FSTU162450
Configurable 4-Bit to 20-Bit Bus Switch with
−2V Undershoot Protection
and 25Ω Series Resistors in Outputs (Preliminary)
General Description
The Fairchild Universal Bus Switch FSTU162450 provides
4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed CMOS
TTL-compatible bus switching. The low On Resistance of
the switch allows inputs to be connected to outputs without
adding propagation delay or generating additional ground
bounce noise.
The FSTU162450 is designed to allow “customer” configu-
ration control of the enable connections. The device can be
organized as either a five 4-bit, four 5-bit, two 10-bit or one
20-bit enable bus switch. Also achieveable are 8-bit and
16-bit enabled configurations (see Functional Description).
The device’s bit configuration is controlled through select
pin logic. (see Truth Table). When OE_x is LOW, Port A_x is
connected to Port B_x. When OE_x is HIGH, the switch is
OPEN.
The A and B Ports are protected against undershoot to
support an extended range to 2.0V below ground.
Fairchild’s integrated Undershoot Hardened Circuit
(UHC) senses undershoot at the I/O and responds by
preventing voltage differentials from developing and turn-
ing the switch on.
Features
s Undershoot protected to −2V (A and B Ports)
s 25Ω switch connection between two ports
s Minimal propagation delay through the switch
s Low l_CC
s Zero bounce in flow-through mode
s Control inputs compatible with TTL level
s See Applications Notes AN-5008 and AN-5021
for UHC details
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Applications Note
Select pins S₀, S₁, S₂ are intended to be used as static
user configurable control pins. The AC performance of
these pins has not been characterized or tested. Switching
of these select pins during system operation may tempo-
rarily disrupt output logic states and/or enable pin controls.
Ordering Code:
Order Number Package Number
Package Description
FSTU162450GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
FSTU162450MTD
(Note 2)
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
UHC is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation DS500423
www.fairchildsemi.com