FSTD32450 Datasheet, PDF(1/13 Page) Fairchild Semiconductor – Configurable 4-Bit to 40-Bit Bus Switch with Selectable Level Shifting (Preliminary)

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FSTD32450 Datasheet, PDF (1/13 Pages) Fairchild Semiconductor – Configurable 4-Bit to 40-Bit Bus Switch with Selectable Level Shifting (Preliminary)

Preliminary

February 2001

Revised August 2001

FSTD32450

Configurable 4-Bit to 40-Bit Bus Switch with

Selectable Level Shifting (Preliminary)

General Description

The Fairchild Universal Bus Switch FSTD32450 provides

4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit...40-bit of high-speed

CMOS TTL-compatible bus switching. The low On Resis-

tance of the switch allows inputs to be connected to out-

puts without adding propagation delay or generating

additional ground bounce noise.

The FSTD32450 is designed to allow âcustomerâ configura-

tion control of the enable connections. The device can be

organized as either a ten 4-bit, eight 5-bit, four 10-bit, two

20-bit or one 40-bit enabled bus switch. Also achievable

are 8-bit and 16-bit enabled configurations (see Functional

Description). The deviceâs bit configuration is controlled

through select pin logic. (see Truth Table). When OEx is

LOW, Port Ax is connected to Port Bx. When OEx is HIGH,

the switch is OPEN.

Another key device feature is the addition of a level shifting

select pin, âS2 and S5â. When S2 and S5 are LOW, the

device behaves as a standard N-MOS switch. When S2

and S5 are HIGH, a diode to VCC is integrated into the cir-

cuit allowing for level shifting between 5V inputs and 3.3V

outputs.

Features

s Voltage level shifting

s 4â¦ switch connection between two ports

s Minimal propagation delay through the switch

s Low lCC

s Zero bounce in flow-through mode

s Control inputs compatible with TTL level

s Packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

Applications Note

Select pins S0, S1, S2, S3, S4 and S5 are intended to be

used as static user configurable control pins. The AC per-

formance of these pins has not been characterized or

tested. Switching of these select pins during system opera-

tion may temporarily disrupt output logic states and/or

enable pin controls.

40-bit configuration can be achieved by connecting the

OE1 and the OE6 pins to together.

Ordering Code:

Order Number Package Number

Package Description

FSTD32450GX

(Note 1)

BGA114A

(Preliminary)

114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[Tape and Reel]

Note 1: BGA package available in Tape and Reel only.

UHCï£ª is a trademark of Fairchild Semiconductor Corporation.

www.fairchildsemi.com

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