FQD1P50TF Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – 500V P-Channel MOSFET

FQD1P50 / FQU1P50
500V P-Channel MOSFET
January 2009
QFET^®
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for electronic lamp ballast based on complimentary
half bridge.
D
D-PAK
G S _{FQD Series}
GDS
Features
• -1.2A, -500V, R_DS(on) = 10.5Ω @V_GS = -10 V
• Low gate charge ( typical 11 nC)
• Low Crss ( typical 6.0 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• RoHS Compliant
I-PAK
FQU Series
G!
S
!
●
●
▶▲
●
!
D
Absolute Maximum Ratings T_C = 25°C unless otherwise noted
Symbol
V_DSS
I_D
I_DM
V_GSS
E_AS
I_AR
E_AR
dv/dt
P_D
T_J, T_STG
T_L
Parameter
Drain-Source Voltage
Drain Current
- Continuous (T_C = 25°C)
- Continuous (T_C = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 3)
Power Dissipation (T_A = 25°C) *
Power Dissipation (T_C = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
Parameter
R_θJC
Thermal Resistance, Junction-to-Case
R_θJA
Thermal Resistance, Junction-to-Ambient *
R_θJA
Thermal Resistance, Junction-to-Ambient
* When mounted on the minimum pad size recommended (PCB Mount)
©2009 Fairchild Semiconductor Corporation
FQD1P50 / FQU1P50
-500
-1.2
-0.76
-4.8
± 30
110
-1.2
3.8
-4.5
2.5
38
0.3
-55 to +150
300
Typ
Max
--
3.29
--
50
--
110
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
°C
Units
°C/W
°C/W
°C/W
Rev. B3, January 2009