FQD12N20LTM Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – 200V Logic Level N-Channel MOSFET

June 2010
FQD12N20LTM_F085
200V Logic Level N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters,
switch mode power supply, motor control.
Features
• 9.0A, 200V, R_DS(on) = 0.28Ω @V_GS = 10 V
• Low gate charge ( typical 16 nC)
• Low Crss ( typical 17 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• Low level gate drive requirement allowing direct
opration from logic drivers
• Qualified to AEC Q101
• RoHS Compliant
D
GS
D-PAK
Absolute Maximum Ratings T_C = 25°C unless otherwise noted
Symbol
V_DSS
I_D
I_DM
V_GSS
I_AR
Parameter
Drain-Source Voltage
Drain Current
Drain Current
- Continuous (T_C = 25°C)
- Continuous (T_C = 100°C)
- Pulsed
Gate-Source Voltage
Avalanche Current
(Note 1)
(Note 1)
dv/dt
P_D
T_J, T_STG
T_L
Peak Diode Recovery dv/dt
(Note 2)
Power Dissipation (T_A = 25°C) *
Power Dissipation (T_C = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds

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FQD12N20LTM_F085
200
9.0
5.7
36
± 20
9.0
5.5
2.5
55
0.44
-55 to +150
300
Units
V
A
A
A
V
A
V/ns
W
W
W/°C
°C
°C
Thermal Characteristics
Symbol
R_θJC
R_θJA
R_θJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
* When mounted on the minimum pad size recommended (PCB Mount)
©2010 Fairchild Semiconductor Corporation
1
FQD12N20LTM_F085 Rev. B
Typ
Max
Units
--
2.27
°C/W
--
50
°C/W
--
110
°C/W
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