FIN1001_04 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – 3.3V LVDS 1-Bit High Speed Differential Driver

December 2001
Revised August 2004
FIN1001
3.3V LVDS 1-Bit High Speed Differential Driver
General Description
This single driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The driver translates LVTTL signal levels to LVDS lev-
els with a typical differential output swing of 350 mV which
provides low EMI at ultra low power dissipation even at
high frequencies. This device is ideal for high speed trans-
fer of clock or data.
The FIN1001 can be paired with its companion receiver,
the FIN1002, or with any other LVDS receiver.
Features
s Greater than 600Mbs data rate
s 3.3V power supply operation
s 0.5ns maximum differential pulse skew
s 1.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Flow-through pinout simplifies PCB layout
s 5-Lead SOT23 package saves space
Ordering Code:
Order Number
FIN1001M5
FIN1001M5X
Package Number
Package Description
MA05B
5-Lead SOT23, JEDEC MO-178, 1.6mm [250 Units on Tape and Reel]
MA05B
5-Lead SOT23, JEDEC MO-178, 1.6mm [3000 Units on Tape and Reel]
Pin Descriptions
Pin Name
D_IN
D_OUT+
D_OUT−
V_CC
GND
NC
Description
LVTTL Data Input
Non-inverting LVDS Driver Output
Inverting LVDS Driver Output
Power Supply
Ground
No Connect
Connection Diagram
Pin Assignment for SOT23
Function Table
Input
D_IN
L
H
H = HIGH Logic Level
Outputs
D_OUT+
D_OUT−
L
H
H
L
L = LOW Logic Level
(Top View)
© 2004 Fairchild Semiconductor Corporation DS500721
www.fairchildsemi.com