FDR856P Datasheet, PDF (1/8 Pages) Fairchild Semiconductor – P-Channel Logic Level Enhancement Mode Field Effect Transistor

March 1998
FDR856P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOT^TM-8 P-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as battery powered circuits or
portable electronics where low in-line power loss, fast
switching and resistance to transients are needed.
Features
- 6.3 A, -30 V, R_DS(ON) =0.025 Ω @ V_GS = -10 V
R_DS(ON) =0.040 Ω @ V_GS = -4.5 V.
SuperSOT^TM-8 package:
small footprint (40% less than SO-8);low profile (1mm
thick);maximum power comperable to SO-8.
High density cell design for extremely low R_DS(ON).
SOT-23
SuperSOT^TM-6
SuperSOT^TM-8
SO-8
SOT-223
SOIC-16
S
D
D
S
856P
G
D
pin 1
D
SuperSOT ^TM-8
D
Absolute Maximum Ratings T_A = 25^oC unless other wise noted
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Maximum Drain Current - Continuous (Note 1a)
- Pulsed
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
R_θJC
Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
5
4
6
3
7
2
8
1
FDR856P
-30
±20
-5.1
-50
1.8
1
0.9
-55 to 150
50
25
Units
V
V
A
W
°C
°C/W
°C/W
FDR856P Rev.B