FDP603AL Datasheet, PDF (1/4 Pages) Fairchild Semiconductor – N-Channel Logic Level Enhancement Mode Field Effect Transistor

April 1998
FDP603AL / FDB603AL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low
voltage applications such as DC/DC converters and high
efficiency switching circuits where fast switching, low in-line
power loss, and resistance to transients are needed.
Features
33
A,
30
V.
R_DS(ON)
R_DS(ON)
=
=
0.022
0.036
Ω
Ω
@
@
V_GS=10 V
V_GS=4.5 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low R_DS(ON).
175°C maximum junction temperature rating.
_________________________________________________________________________________
D
G
S
Absolute Maximum Ratings T_C = 25°C unless otherwise noted
Symbol Parameter
FDP603AL
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Drain Current - Continuous
- Pulsed
(Note 1)
P_D
Total Power Dissipation @ T_C = 25°C
Derate above 25°C
T_J,T_STG
T_L
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
THERMAL CHARACTERISTICS
R_θJC
Thermal Resistance, Junction-to-Case
R_θJA
Thermal Resistance, Junction-to-Ambient
30
±20
33
100
50
0.33
-65 to 175
275
FDB603AL
3
62.5
© 1998 Fairchild Semiconductor Corporation
Units
V
V
A
W
W/°C
°C
°C
°C/W
°C/W
FDP603AL Rev.D