FDN338P Datasheet, PDF (1/4 Pages) Fairchild Semiconductor – P-Channel Logic Level Enhancement Mode Field Effect Transistor

March 1998
FDN338P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOT^TM-3 P-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited for
low voltage applications in notebook computers, portable
phones, PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are needed
in a very small outline surface mount package.
Features
-1.6 A, -20 V, R_DS(ON) = 0.13 Ω @ V_GS = -4.5 V
R_DS(ON) = 0.18 Ω @ V_GS = -2.5 V.
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOT^TM-3 design for
superior thermal and electrical capabilities.
High density cell design for extremely low R_DS(ON).
Exceptional on-resistance and maximum DC current
capability.
SuperSOT^TM-3
SuperSOT^TM-6
SuperSOT^TM-8
SO-8
SOT-223
SOIC-16
D
338
S
SuperSOT ^TM-3
G
D
G
S
Absolute Maximum Ratings T_A = 25^oC unless other wise noted
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Drain/Output Current - Continuous
- Pulsed
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
R_θJC
Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
FDN338P
-20
±8
-1.6
-5
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
FDN338P Rev.D