FDL100N50F Datasheet, PDF (1/8 Pages) Fairchild Semiconductor – N-Channel MOSFET,FRFET 500V, 100A, 0.055Ω

FDL100N50F
N-Channel MOSFET,FRFET
500V, 100A, 0.055Ω
Features
• R_DS(on) = 0.043Ω ( Typ.)@ V_GS = 10V, I_D = 50A
• Low gate charge ( Typ. 238nC)
• Low Crss ( Typ. 64pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• RoHS Compliant
May 2009
UniFET^TM
Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies and active power factor
correction.
D
G DS
TO-264
FDL Series
MOSFET Maximum Ratings T_C = 25^oC unless otherwise noted
Symbol
V_DSS
V_GSS
I_D
I_DM
E_AS
I_AR
E_AR
dv/dt
P_D
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Drain Current
-Continuous (T_C = 25^oC)
-Continuous (T_C = 100^oC)
- Pulsed
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
(T_C = 25^oC)
- Derate above 25^oC
T_J, T_STG
T_L
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purpose,
1/8” from Case for 5 Seconds
*Drain current limited by maximum junction temperature
Thermal Characteristics
Symbol
R_θJC
R_θCS
R_θJA
Parameter
Thermal Resistance, Junction to Case
Thermal Resistance, Case to Sink Typ.
Thermal Resistance, Junction to Ambient
G
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 3)
S
FDL100N50F
500
±30
100
60
400
5000
100
73.5
20
2500
20
-55 to +150
300
Min.
-
0.1
-
Max.
0.05
-
30
Units
V
V
A
A
mJ
A
mJ
V/ns
W
W/^oC
o_C
o_C
Units
o_C/W
©2009 Fairchild Semiconductor Corporation
1
FDL100N50F Rev. A
www.fairchildsemi.com