FDG8842CZ Datasheet, PDF (1/8 Pages) Fairchild Semiconductor – Complementary PowerTrench® MOSFET

April 2007
FDG8842CZ
tm
Complementary PowerTrench^® MOSFET
Q1:30V,0.75A,0.4Ω; Q2:–25V,–0.41A,1.1Ω
Features
Q1: N-Channel
„ Max r_DS(on) = 0.4Ω at V_GS = 4.5V, I_D = 0.75A
„ Max r_DS(on) = 0.5Ω at V_GS = 2.7V, I_D = 0.67A
Q2: P-Channel
„ Max r_DS(on) = 1.1Ω at V_GS = –4.5V, I_D = –0.41A
„ Max r_DS(on) = 1.5Ω at V_GS = –2.7V, I_D = –0.25A
„ Very low level gate drive requirements allowing direct
operation in 3V circuits(V_GS(th) <1.5V)
„ Very small package outline SC70-6
„ RoHS Compliant
General Description
These N & P-Channel logic level enhancement mode field effect
transistors are produced using Fairchild’s proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage applica-
tions as a replacement for bipolar digital transistors and small
signal MOSFETs. Since bias resistors are not required, this dual
digital FET can replace several different digital transistors, with
different bias resistor values.
S2
G2
D1
Q1
S1
D1
G1
D2
G2
G1
S1
Q2
D2
S2
SC70-6
Pin 1
MOSFET Maximum Ratings T_A = 25°C unless otherwise noted
Symbol
V_DS
V_GS
I_D
P_D
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous
-Pulsed
Power Dissipation for Single Operation
T_J, T_STG
Operating and Storage Junction Temperature Range
Thermal Characteristics
R_θJA
R_θJA
Thermal Resistance, Junction to Ambient Single operation
Thermal Resistance, Junction to Ambient Single operation
Package Marking and Ordering Information
Device Marking
.42
Device
FDG8842CZ
Reel Size
7”
(Note 1a)
(Note 1b)
Q1
Q2
30
–25
±12
–8
0.75
–0.41
2.2
–1.2
0.36
0.30
–55 to +150
Units
V
V
A
W
°C
(Note 1a)
350
(Note 1b)
415
°C/W
Tape Width
8mm
Quantity
3000 units
©2007 Fairchild Semiconductor Corporation
1
FDG8842CZ Rev.B
www.fairchildsemi.com