FDG6321C Datasheet, PDF (1/12 Pages) Fairchild Semiconductor – Dual N & P Channel Digital FET

November 1998
FDG6321C
Dual N & P Channel Digital FET
General Description
These dual N & P-Channel logic level enhancement mode field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
This device has been designed especially for low voltage
applications as a replacement for bipolar digital transistors and
small signal MOSFETS. Since bias resistors are not required,
this dual digital FET can replace several different digital
transistors, with different bias resistor values.
Features
N-Ch 0.50 A, 25 V, R_DS(ON) = 0.45 Ω @ V_GS= 4.5V.
R_DS(ON) = 0.60 Ω @ V_GS= 2.7 V.
P-Ch -0.41 A, -25 V,R_DS(ON) = 1.1 Ω @ V_GS= -4.5V.
R_DS(ON) = 1.5 Ω @ V_GS= -2.7V.
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct
operation in 3 V circuits(V_GS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
SC70-6
SOT-23
SuperSOT^TM-6
SOT-8
SO-8
SOIC-14
S2
G2
D1 _.21
SC70-6
D2
G1
S1
1
6
2
5
3
4
Absolute Maximum Ratings T_A = 25^oC unless otherwise noted
Symbol Parameter
N-Channel
V_DSS
Drain-Source Voltage
25
V_GSS
Gate-Source Voltage
8
I_D
Drain Current - Continuous
0.5
- Pulsed
1.5
P_D
T_J,T_STG
ESD
Maximum Power Dissipation
(Note 1)
Operating and Storage Temperature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1)
0.3
-55 to 150
6
415
P-Channel
-25
-8
-0.41
-1.2
Units
V
V
A
W
°C
kV
°C/W
© 1998 Fairchild Semiconductor Corporation
FDG6321C Rev. D