FDG6318PZ Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – Dual P-Channel, Digital FET

January 2003
FDG6318PZ
Dual P-Channel, Digital FET
General Description
These dual P-Channel logic level enhancement mode
MOSFET are produced using Fairchild Semiconductor’s
especially tailored to minimize on-state resistance. This
device has been designed especially for bipolar digital
transistors and small signal MOSFETS
Applications
• Battery management
Features
• -0.5A, -20V. r_DS(ON) = 780mΩ (Max)@ V_GS = -4.5 V
r_DS(ON) = 1200mΩ (Max) @ V_GS = -2.5 V
• Very low level gate drive requirements allowing direct
operation in 3V circuits (V_GS(TH) < 1.5V).
• Gate-Source Zener for ESD ruggedness (>1.4kV Human
Body Model).
• Compact industry standard SC-70-6 surface mount
package.
S
G
D
S 1 or 4
6 or 3 D
Pin 1
D
G
S
G 2 or 5
D 3 or 6
5 or 2 G
4 or 1 S
SC70-6
The pinouts are symmetrical; pin1 and pin 4 are interchangeable.
MOSFET Maximum Ratings T_A=25°C unless otherwise noted
Symbol
V_DSS
V_GS
I_D
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Continuous (T_C = 25^oC, V_GS = - 4.5V)
Continuous (T_C = 100^oC, V_GS = - 2.5V)
Pulsed
Ratings
-20
±12
-0.5
-0.3
Figure 4
P_D
Power dissipation
0.3
Derate above 25°C
2.4
T_J, T_STG
ESD
Operating and Storage Temperature
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model ( 100pF / 1500Ω )
-55 to 150
1.4
Units
V
V
A
A
W
mW/^oC
o_C
kV
Thermal Characteristics
R_θJA
Thermal Resistance Junction to Ambient (Note 1)
Package Marking and Ordering Information
Device Marking
.68
Device
FDG6318PZ
Package
SC70-6
Reel Size
7”
415
Tape Width
8 mm
o_C/W
Quantity
3000
©2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B