FDG6318P Datasheet, PDF (1/5 Pages) Fairchild Semiconductor – Dual P-Channel, Digital FET

January 2003
FDG6318P
Dual P-Channel, Digital FET
General Description
These dual P-Channel logic level enhancement mode
MOSFET are produced using Fairchild Semiconductor’s
advanced PowerTrench process that has been
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage
applications as a replacement for bipolar digital
transistors and small signal MOSFETS.
Applications
• Battery management
Features
• –0.5 A, –20 V.
RDS(ON) = 780 mΩ @ VGS = –4.5 V
RDS(ON) = 1200 mΩ @ VGS = –2.5 V
• Very low level gate drive requirements allowing direct
operation in 3V circuits (VGS(th) < 1.5V).
• Compact industry standard SC70-6 surface mount
package
S
G
D
S 1 or 4
Pin 1
D
G
S
G 2 or 5
D 3 or 6
SC70-6
The pinouts are symmetrical; pin 1 and pin 4 are interchangeable.
6 or 3 D
5 or 2 G
4 or 1 _S
Absolute Maximum Ratings TA=25^oC unless otherwise noted
Symbol
Parameter
VDSS
VGSS
ID
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
(Note 1)
PD
TJ, TSTG
Power Dissipation for Single Operation
(Note 1)
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
.38
FDG6318P
7’’
Ratings
–20
±12
–0.5
–1.8
0.3
–55 to +150
415
Tape width
8mm
Units
V
V
A
W
°C
°C/W
Quantity
3000 units
2003 Fairchild Semiconductor Corporation
FDG6318P Rev C (W)