FDG6313N Datasheet, PDF (1/5 Pages) Fairchild Semiconductor – Dual N-Channel, Digital FET

April 2002
FDG6313N
Dual N-Channel, Digital FET
General Description
These dual N-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small
signal MOSFETs.
Features
25 V, 0.50 A continuous, 1.5 A peak.
R_DS(ON) = 0.45 Ω @ V_GS= 4.5 V,
R_DS(ON) =0.60 Ω @ V_GS= 2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (V_GS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
Compact industry standard SC70-6 surface
mount package.
SC70-6
SOT-23
SuperSOT^TM-6
SuperSOT^TM-8
SO-8
SOT-223
S2
G2
D1 _.33
SC70-6
D2
G1
S1
1 or 4 *
2 or 5
3 or 6
* The pinouts are symmetrical; pin 1 and 4 are interchangeable.
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
Absolute Maximum Ratings T_A = 25°C unless otherwise noted
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage
I_D
Drain/Output Current - Continuous
- Pulsed
P_D
T_J,T_STG
ESD
Maximum Power Dissipation
(Note 1)
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100 pF / 1500 Ω)
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient
FDG6313N
25
- 0.5 to +8
0.5
1.5
0.3
-55 to 150
6.0
415
6 or 3
5 or 2
4 or 1 *
Units
V
V
A
W
°C
kV
°C/W
FDG6313N Rev.A