FDG314P Datasheet, PDF (1/5 Pages) Fairchild Semiconductor – Digital FET, P-Channel

July 2000
FDG314P
Digital FET, P-Channel
General Description
This P-Channel enhancement mode field effect
transistor is produced using Fairchild Semiconductor’s
proprietary, high cell density, DMOS technology. This
very high density process is tailored to minimize on-
state resistance at low gate drive conditions. This
device is designed especially for battery power
applications such as notebook computers and cellular
phones. This device has excellent on-state resistance
even at gate drive voltages as low as 2.5 volts.
Applications
• Power Management
• Load switch
• Signal switch
Features
• -0.65 A, -25 V. R_DS(ON) = 1.1 Ω @ V_GS = -4.5 V
R_DS(ON) = 1.5 Ω @ V_GS = -2.7 V.
• Very low gate drive requirements allowing direct
operation in 3V cirucuits (V_GS(th) <1.5 V).
• Gate-Source Zener for ESD ruggedness
(>6 kV Human Body Model).
• Compact industry standard SC70-6 surface mount
package.
S
D
D
SC70-6
G
D
D
1
6
2
5
3
4
Absolute Maximum Ratings T_A = 25°C unless otherwise noted
Symbol
Parameter
VDSS
VGSS
ID
PD
TJ, Tstg
ESD
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
(Note 1a)
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
Operating and Storage Junction Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf/1500 Ohm)
Ratings
-25
±8
-0.65
-1.8
0.75
0.48
-55 to +150
6.0
Thermal Characteristics
R_θJA
Thermal Resistance, Junction-to-Ambient
(Note 1b)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
.14
FDG314P
7’’
260
Tape Width
8mm
Units
V
V
A
W
°C
kV
°C/W
Quantity
3000 units
2000 Fairchild Semiconductor International
FDG314P Rev.C