FDD6030L Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – N-Channel Logic Level Enhancement Mode Field Effect Transistor

July 1999
ADVANCE INFORMATION
FDD6030L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild’s
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
DC/DC converters and high efficiency switching circuits
where fast switching, low in-line power loss, and
resistance to transients are needed.
Features
• 50 A, 30 V. R_DS(ON) = 0.0135 Ω @ V_GS = 10 V
R_DS(ON) = 0.0200 Ω @ V_GS = 4.5 V.
• Low gate charge.
• Fast switching speed.
• Low Crss.
D
G
S
TO-252
D
G
S
Absolute Maxim um Ratings ^TC^{=25oC unless otherwise noted}
Symbol
VDSS
VGSS
ID
PD
TJ, Tstg
Parameter
Drain-Source Voltage
Gate-Source Voltage
Maximum Drain Current -Continuous
(Note 1)
(Note 1a)
Maximum Drain Current -Pulsed
Maximum Power Dissipation @ TC = 25^oC (Note 1)
TA = 25^oC
(Note 1a)
TA = 25^oC
(Note 1b)
Operating and Storage Junction Temperature Range
Thermal Characteristics
R_θJC
R_θJA
Thermal Resistance, Junction-to- Case
Thermal Resistance, Junction-to- Ambient
(Note 1)
(Note 1a)
(Note 1b)
Ratings
30
±²⁰
50
12
150
60
3.2
1.3
-55 to +150
2.1
39
96
Package Marking and Ordering Information
Device Marking
Device
Reel Size
FDD6030L
FDD6030L
13’’
©1999 Fairchild Semiconductor Corporation
Tape width
16mm
Units
V
V
A
W
°^C
°^C/W
°^C/W
°^C/W
Quantity
2500
FDD6030L Rev. A1