FDC654P Datasheet, PDF (1/4 Pages) Fairchild Semiconductor – P-Channel Enhancement Mode Field Effect Transistor

March 1998
FDC654P
P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low
voltage applications such as cellular phone and notebook
computer power management and other battery powered
circuits where high-side switching, and low in-line power
loss are needed in a very small outline surface mount
package.
Features
-3.6 A, -30 V. R_DS(ON) = 0.075 Ω @ V_GS = -10 V
R_DS(ON) = 0.125 Ω @ V_GS = -4.5 V.
SuperSOT^TM-6 package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R_DS(ON).
Exceptional on-resistance and maximum DC current capability.
SOT-23
SuperSOT^TM-6
SuperSOT^TM-8
S
D
D
.654
G
D
SuperSOT ^TM -6 ^{pin 1 D}
SO-8
SOT-223
SOIC-16
1
6
2
5
3
4
Absolute Maximum RatingsT_A = 25°C unless otherwise note
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Drain Current - Continuous
- Pulsed
(Note 1a)
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient
R_θJC
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
© 1998 Fairchild Semiconductor Corporation
FDC654P
-30
±20
-3.6
-10
1.6
0.8
-55 to 150
78
30
Units
V
V
A
W
°C
°C/W
°C/W
FDC654P Rev.C