FDC633N Datasheet, PDF (1/4 Pages) Fairchild Semiconductor – N-Channel Enhancement Mode Field Effect Transistor

March 1998
FDC633N
N-Channel Enhancement Mode Field Effect Transistor
General Description
This N-Channel enhancement mode power field effect
transistors is produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
tailored to minimize on-state resistance. These devices are
particularly suited for low voltage applications in notebook
computers, portable phones, PCMICA cards, and other
battery powered circuits where fast switching,low in-line
power loss and resistance to transients are needed in a very
small outline surface mount package.
Features
5.2 A, 30 V. R_DS(ON) = 0.042 Ω @ V_GS = 4.5 V
R_DS(ON) = 0.054 Ω @ V_GS = 2.5 V.
SuperSOT^TM-6 package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R_DS(ON).
Exceptional on-resistance and maximum DC current
capability.
SOT-23
SuperSOT^TM-6
SuperSOT^TM-8
SO-8
SOT-223
SOIC-16
S
D
D
.633
G
D
SuperSOT ^TM -6 ^{pin 1 D}
Absolute Maximum Ratings T_A = 25°C unless otherwise noted
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Drain Current - Continuous
- Pulsed
(Note 1a)
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
R_θJC
Thermal Resistance, Junction-to-Case
(Note 1)
© 1998 Fairchild Semiconductor Corporation
1
6
2
5
3
4
FDC633N
30
±8
5.2
16
1.6
0.8
-55 to 150
78
30
Units
V
V
A
W
°C
°C/W
°C/W
FDC633N Rev.C