FDC6321C Datasheet, PDF (1/11 Pages) Fairchild Semiconductor – Dual N & P Channel , Digital FET

April 1999
FDC6321C
Dual N & P Channel , Digital FET
General Description
These dual N & P Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
digital transistors in load switching applications. Since bias
resistors are not required this dual digital FET can replace
several digital transistors with different bias resistors.
Features
N-Ch 25 V, 0.68 A, R_DS(ON) = 0.45 Ω @ V_GS= 4.5 V
P-Ch -25 V, -0.46 A, R_DS(ON) = 1.1 Ω @ V_GS= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits. V_GS(th) < 1.0V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple dual NPN & PNP digital transistors.
SOT-23
SuperSOT^TM-6
Mark:.321
D2
S1
D1
SuperSOT^TM-8
SuperSOT ^TM-6
G2
S2
G1
SO-8
SOT-223
SOIC-16
4
3
5
2
6
1
Absolute Maximum Ratings T_A = 25^oC unless other wise noted
Symbol Parameter
N-Channel
V_DSS, V_CC Drain-Source Voltage, Power Supply Voltage
25
V_GSS, V_IN Gate-Source Voltage,
8
I_D, I_O
Drain/Output Current - Continuous
0.68
- Pulsed
2
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
T_J,T_STG
ESD
Operating and Storage Tempature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
R_θJC
Thermal Resistance, Junction-to-Case (Note 1)
0.9
0.7
-55 to 150
6
140
60
P-Channel
-25
-8
-0.46
-1.5
© 1999 Fairchild Semiconductor Corporation
Units
V
V
A
W
°C
kV
°C/W
°C/W
FDC6321C.RevB