FDC6304P Datasheet, PDF (1/4 Pages) Fairchild Semiconductor – Digital FET, Dual P-Channel

July 1997
FDC6304P
Digital FET, Dual P-Channel
General Description
These P-Channel enhancement mode field effect transistor are
produced using Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is tailored to minimize
on-state resistance at low gate drive conditions. This device is
designed especially for application in battery power applications
such as notebook computers and cellular phones. This device
has excellent on-state resistance even at gate drive voltages as
low as 2.5 volts.
Features
-25 V, -0.46 A continuous, -1.0 A Peak.
R_DS(ON) = 1.5 Ω @ V_GS= -2.7 V
R_DS(ON) = 1.1 Ω @ V_GS = -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V_GS(th) < 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model.
SOT-23
SuperSOT^TM-6
Mark: .304
SuperSOT^TM-8
SO-8
SOT-223
SOIC-16
Absolute Maximum Ratings T_A = 25^oC unless other wise noted
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage
I_D
Drain Current
- Continuous
- Pulsed
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
T_J,T_STG
ESD
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
R_θJC
Thermal Resistance, Junction-to-Case
(Note 1)
© 1997 Fairchild Semiconductor Corporation
4
3
5
2
6
1
FDC6304P
-25
-8
-0.46
-1
0.9
0.7
-55 to 150
6.0
140
60
Units
V
V
A
W
°C
kV
°C/W
°C/W
FDC6304P Rev.D