FDC6303N Datasheet, PDF (1/4 Pages) Fairchild Semiconductor – Digital FET, Dual N-Channel

August 1997
FDC6303N
Digital FET, Dual N-Channel
General Description
These dual N-Channel logic level enhancement mode field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. This device has been designed especially for
low voltage applications as a replacement for digital
transistors in load switching applications. Since bias
resistors are not required this one N-Channel FET can
replace several digital transistors with different bias
resistors like the IMHxA series.
Features
25 V, 0.68 A continuous, 2 A Peak.
R_DS(ON) = 0.6 Ω @ V_GS = 2.7 V
R_DS(ON) = 0.45 Ω @ V_GS= 4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V_GS(th) < 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple NPN digital transistors (IMHxA series)
with one DMOS FET.
SOT-23
SuperSOT^TM-6
SuperSOT^TM-8
Mark: .303
SO-8
SOT-223
SOIC-16
4
3
5
2
6
1
Absolute Maximum Ratings T_A = 25°C unless otherwise noted
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage
I_D
Drain Current
- Continuous
- Pulsed
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
T_J,T_STG
ESD
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
R_θJC
Thermal Resistance, Junction-to-Case
(Note 1)
© 1997 Fairchild Semiconductor Corporation
FDC6303N
25
8
0.68
2
0.9
0.7
-55 to 150
6.0
140
60
Units
V
V
A
W
°C
kV
°C/W
°C/W
FDC6303N Rev.C