FDC6301N_01 Datasheet, PDF (1/5 Pages) Fairchild Semiconductor – Dual N-Channel , Digital FET

September 2001
FDC6301N
Dual N-Channel , Digital FET
General Description
These dual N-Channel logic level enhancement mode field
effect transistors are produced using Fairchild 's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
This device has been designed especially for low voltage
applications as a replacement for digital transistors. Since bias
resistors are not required, these N-Channel FET's can replace
several digital transistors, with a variety of bias resistors.
Features
25 V, 0.22 A continuous, 0.5 A Peak.
R_DS(ON) = 5 Ω @ V_GS= 2.7 V
R_DS(ON) = 4 Ω @ V_GS= 4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V_GS(th) < 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model.
SOT-23
SuperSOT^TM-6
Mark: .301
SuperSOT^TM-8
4
5
6
SO-8
SOT-223
SOIC-16
3
2
IN
1
INVERTER APPLICATION
D
Vcc
OUT
G
S
GND
Absolute Maximum Ratings T_A = 25^oC unless other wise noted
Symbol Parameter
V_DSS, V_CC
V_GSS, V_IN
I_D, I_OUT
Drain-Source Voltage, Power Supply Voltage
Gate-Source Voltage, V_IN
Drain/Output Current - Continuous
- Pulsed
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
T_J,T_STG
ESD
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
R_θJC
Thermal Resistance, Junction-to-Case
(Note 1)
© 2001 Fairchild Semiconductor Corporation
FDC6301N
25
- 0.5 to +8
0.22
0.5
0.9
0.7
-55 to 150
6.0
140
60
Units
V
V
A
W
°C
kV
°C/W
°C/W
FDC6301N Rev.D