FCH190N65F_F085_15 Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – N-Channel SuperFET II FRFET MOSFET

FCH190N65F_F085
December
2014
N-Channel SuperFET II FRFET MOSFET
650 V, 20.6 A, 190 mΩ
Features
„ Typical R_DS(on) = 148 mΩ at V_GS = 10 V, I_D = 10 A
„ Typical Q_g(tot) = 63 nC at V_GS = 10V, I_D = 10 A
„ UIS Capability
„ Qualified to AEC Q101
„ RoHS Compliant
Description
G
D
S
D
G
TO-247
S
SuperFET® II MOSFET is Fairchild Semiconductor’s brand-new
high voltage super-junction (SJ) MOSFET family that is utilizing
charge balance technology for outstanding low on-resistance
and lower gate charge performance. This technology is tailored
to minimize conduction loss, provide superior switching
performance, dv/dt rate and higher avalanche energy.
Consequently SuperFETII is very well suited for the Soft switching
and Hard Switching topologies like High Voltage Full Bridge and
Half Bridge DC-DC, Interleaved Boost PFC, Boost PFC for HEV-EV
automotive.
SuperFET II FRFET® MOSFET’s optimized body diode reverse
recovery performance can remove additional component and
improve system reliability.
For current package drawing, please refer to the Fairchild web‐
site at https://www.fairchildsemi.com/package‐drawings/TO/
TO247A03.pdf
Application
„ Automotive On Board Charger
„ Automotive DC/DC converter for HEV
Maximum Ratings T_C = 25°C unless otherwise noted
Symbol
Parameter
V_DSS
V_GS
I_D
Drain to Source Voltage
Gate to Source Voltage
Drain Current - Continuous (V_GS=10) (Note 1)
Pulsed Drain Current
E_AS
dv/dt
Single Pulse Avalanche Rating
MOSFET dv/dt
Peak Diode Recovery dv/dt
(Note 2)
(Note 3)
Power Dissipation
P_D
Derate Above 25^oC
T_J, T_STG Operating and Storage Temperature
R_θJC
Maximum Thermal Resistance Junction to Case
R_θJA
Maximum Thermal Resistance Junction to Ambient
(Note 4)
Ratings
650
±20
20.6
See Fig 4
400
100
50
208
1.67
-55 to + 150
0.6
40
Units
V
V
A
A
mJ
V/ns
W
W/^oC
o_C
o_C/W
o_C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FCH190N65F FCH190N65F_F085
TO-247
-
-
30
Notes:
1: Current is limited by bondwire configuration.
2: Starting T_J = 25°C, L = 50mH, I_AS = 4A, V_DD = 100V during inductor charging and V_DD = 0V during time in avalanche.
3: I_SD ≤ 10A, di/dt ≤ 200 A/us, V_DD ≤ 380V, starting T_J = 25°C.
4: R_θJA is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder
mounting surface
presented here is
of the
based
drain pins. R_θJC is
on mounting on a 1
guaranteed by design,
in² pad of 2oz copper.
while
R_θJAis
determined
by
the
board
design.
The maximum rating
©2014 Fairchild Semiconductor Corporation
1
FCH190N65F_F085 Rev. B1
www.fairchildsemi.com