DM74LS393 Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Dual 4-Bit Binary Counter

August 1986
Revised March 2000
DM74LS393
Dual 4-Bit Binary Counter
General Description
Each of these monolithic circuits contains eight master-
slave flip-flops and additional gating to implement two indi-
vidual four-bit counters in a single package. The
DM74LS393 comprises two independent four-bit binary
counters each having a clear and a clock input. N-bit binary
counters can be implemented with each package providing
the capability of divide-by-256. The DM74LS393 has paral-
lel outputs from each counter stage so that any submultiple
of the input count frequency is available for system-timing
signals.
Features
s Dual version of the popular DM74LS93
s DM74LS393 dual 4-bit binary counter with individual
clocks
s Direct clear for each 4-bit counter
s Dual 4-bit versions can significantly improve system
densities by reducing counter package count by 50%
s Typical maximum count frequency 35 MHz
s Buffered outputs reduce possibility of collector commu-
tation
Ordering Code:
Order Number Package Number
Package Description
DM74LS393M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS373N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Counter Sequence (Each Counter)
Outputs
Count
Q_D
Q_C
Q_B
Q_A
0
L
L
L
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
10
H
L
H
L
11
H
L
H
H
12
H
H
L
L
13
H
H
L
H
14
H
H
H
L
15
H
H
H
H
H = HIGH Logic Level
L = LOW Logic Level
© 2000 Fairchild Semiconductor Corporation DS006434
www.fairchildsemi.com