DM74LS243 Datasheet, PDF (1/5 Pages) Fairchild Semiconductor – Quadruple Bus Transceiver

August 1986
Revised January 2000
DM74LS243
Quadruple Bus Transceiver
General Description
This four data line transceiver is designed for asynchro-
nous two-way communications between data buses. It can
be used to drive terminated lines down to 133Ω.
Features
s Two-way asynchronous communication between data
buses
s PNP inputs reduce DC loading on bus line
s Hysteresis at data inputs improves noise margin
Ordering Code:
Order Number Package Number
Package Description
DM74LS243M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS243N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Control
Data Port
Inputs
Status
G AB
GBA
A
B
H
H
O
I
L
H
(Note 1) (Note 1)
H
L
ISOLATED
L
L
I
O
I = Input
O = Output
H = HIGH Logic Level
L = LOW Logic Level
Note 1: Possibly destructive oscillation may occur if the transceivers are
enabled in both directions at once.
© 2000 Fairchild Semiconductor Corporation DS006412
www.fairchildsemi.com