DM74ALS580A Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Octal D-Type Transparent Latch with 3-STATE Outputs

April 1984
Revised February 2000
DM74ALS580A
Octal D-Type Transparent Latch with 3-STATE Outputs
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight inverting latches of the DM74ALS580A are trans-
parent D-type latches. While the enable (G) is HIGH the Q
outputs will follow the complement of the data (D) inputs.
When the enable is taken LOW the output will be latched at
the complement of the level of the data that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and V_CC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s 3-STATE buffer-type outputs drive bus lines directly
Ordering Code:
Order Number Package Number
Package Description
DM74ALS580AWM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS580AN
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006229
www.fairchildsemi.com