DM74ALS174 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – Hex/Quad D-Type Flip-Flops with Clear

September 1986
Revised February 2000
DM74ALS174 • DM74ALS175
Hex/Quad D-Type Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. Both have an asynchro-
nous clear input, and the quad (DM74ALS175) version fea-
tures complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
Features
s Advanced oxide-isolated ion-implanted Schottky TTL
process
s Pin and functional compatible with LS family counterpart
s Typical clock frequency maximum is 80 MHz
s Switching performance guaranteed over full temperature
and V_CC supply range
Ordering Code:
Ordering Code Package Number
Package Description
DM74ALS174M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS174SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS174N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74ALS175M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS175N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
DM74ALS174
DM74ALS175
© 2000 Fairchild Semiconductor Corporation DS006112
www.fairchildsemi.com