DM74ALS109A Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Dual J-K Positive-Edge-Triggered Flip-Flop

April 1984
Revised February 2000
DM74ALS109A
Dual J-K Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The DM74ALS109A is a dual edge-triggered flip-flop. Each
flip-flop has individual J, K, clock, clear and preset inputs,
and also complementary Q and Q outputs.
Information at input J or K is transferred to the Q output on
the positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the J, K input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
The J-K design allows operation as a D flip-flop by tying the
J and K inputs together.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and V_CC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin for pin compatible with Schottky
and LS TTL counterpart
s Improved AC performance over LS109 at approximately
half the power
Ordering Code:
Order Number Package Number
Package Description
DM74ALS109AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS109AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CK J K
Q
Q
LHXXX
H
L
HL XXX
L
H
L L X X X H (Note 1) H (Note 1)
HH ↑ L L
L
H
HH ↑HL
TOGGLE
HH ↑ LH
Q₀
Q₀
HH ↑HH
H
L
HH L XX
Q₀
Q₀
L = LOW State
H = HIGH State
X = Don't Care
↑ = Positive Edge Transition,
Q₀ = Previous Condition of Q
Note 1: This condition is nonstable; it will not persist when present and
clear inputs return to their inactive (HIGH) level. The output levels in this
condition are not guaranteed to meet the V_OH specification.
© 2000 Fairchild Semiconductor Corporation DS006196
www.fairchildsemi.com