DM74ALS09 Datasheet, PDF (1/4 Pages) Fairchild Semiconductor – Quad 2-Input AND Gate with Open Collector Outputs

September 1986
Revised February 2000
DM74ALS09
Quad 2-Input AND Gate with Open Collector Outputs
General Description
This device contains four independent gates, each of which
performs the logic AND function. The open-collector out-
puts require external pull-up resistors for proper logical
operation.
Pull-Up Resistor Equations
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and V_CC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
s Improved AC performance over Schottky and low power
Schottky counterparts
Where:
N₁ (I_OH) = total maximum output HIGH current
for all outputs tied to pull-up resistor
N₂ (I_IH) = total maximum input HIGH current
for all inputs tied to pull-up resistor
N₃ (I_IL) = total maximum input LOW current for
all inputs tied to pull-up resistor
Ordering Code:
Order Number Package Number
Package Description
DM74ALS09M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS09N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y = AB
Inputs
A
B
L
L
L
H
H
L
H
H
Output
Y
L
L
L
H
H = HIGH Logic Level
L = LOW Logic Level
© 2000 Fairchild Semiconductor Corporation DS006179
www.fairchildsemi.com