CD4047BC_02 Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – Low Power Monostable/Astable Multivibrator

October 1987
Revised March 2002
CD4047BC
Low Power Monostable/Astable Multivibrator
General Description
The CD4047B is capable of operating in either the
monostable or astable mode. It requires an external capac-
itor (between pins 1 and 3) and an external resistor
(between pins 2 and 3) to determine the output pulse width
in the monostable mode, and the output frequency in the
astable mode.
Astable operation is enabled by a high level on the astable
input or low level on the astable input. The output fre-
quency (at 50% duty cycle) at Q and Q outputs is deter-
mined by the timing components. A frequency twice that of
Q is available at the Oscillator Output; a 50% duty cycle is
not guaranteed.
Monostable operation is obtained when the device is trig-
gered by LOW-to-HIGH transition at + trigger input or
HIGH-to-LOW transition at − trigger input. The device can
be retriggered by applying a simultaneous LOW-to-HIGH
transition to both the + trigger and retrigger inputs.
A high level on Reset input resets the outputs Q to LOW, Q
to HIGH.
Features
s Wide supply voltage range: 3.0V to 15V
s High noise immunity: 0.45 V_DD (typ.)
s Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
Special Features
s Low power consumption: special CMOS oscillator
configuration
s Monostable (one-shot) or astable (free-running)
operation
s True and complemented buffered outputs
s Only one external R and C required
Monostable Multivibrator
Features
s Positive- or negative-edge trigger
s Output pulse width independent of trigger pulse duration
s Retriggerable option for pulse width expansion
s Long pulse widths possible using small RC components
by means of external counter provision
s Fast recovery time essentially independent of pulse
width
s Pulse-width accuracy maintained at duty cycles
approaching 100%
Astable Multivibrator Features
s Free-running or gatable operating modes
s 50% duty cycle
s Oscillator output available
s Good astable frequency stability
typical= ±2% + 0.03%/°C @ 100 kHz
frequency= ±0.5% + 0.015%/°C @ 10 kHz
deviation (circuits trimmed to frequency V_DD = 10V
±10%)
Applications
• Frequency discriminators
• Timing circuits
• Time-delay applications
• Envelope detection
• Frequency multiplication
• Frequency division
Ordering Code:
Order Number Package Number
Package Description
CD4047BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4047BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation DS005969
www.fairchildsemi.com