CD4015BC Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Dual 4-Bit Static Shift Register

October 1987
Revised January 1999
CD4015BC
Dual 4-Bit Static Shift Register
General Description
The CD4015BC contains two identical, 4-stage, serial-
input/parallel-output registers with independent “Data”,
“Clock,” and “Reset” inputs. The logic level present at the
input of each stage is transferred to the output of that stage
at each positive-going clock transition. A logic high on the
“Reset” input resets all four stages covered by that input.
All inputs are protected from static discharge by a series
resistor and diode clamps to V_DD and V_SS.
Features
s Wide supply voltage range: 3.0V to 18V
s High noise immunity: 0.45 V_DD (typ.)
s Low power TTL: Fan out of 2 driving 74L
compatibility: or 1 driving 74LS
s Medium speed operation: 8 MHz (typ.) clock rate
s Fully static design: @V_DD − V_SS = 10V
Applications
• Serial-input/parallel-output data queueing
• Serial to parallel data conversion
• General purpose register
Ordering Code:
Order Number Package Number
Package Description
CD4015BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4015BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP and SOIC
CL
D
^{(Note 1)}
0
1
X
X
X
R Q₁ Q_n
0
0 Q_n−1
0
1 Q_n−1
0 Q₁ Q_n (No change)
100
X = Don't Care Case
Note 1: Level Change
© 1999 Fairchild Semiconductor Corporation DS005948.prf
www.fairchildsemi.com