BSS110 Datasheet, PDF (1/10 Pages) NXP Semiconductors – P-channel enhancement mode vertical D-MOS transistor

May 1999
BSS84 / BSS110
P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is designed to minimize on-state resistance, provide
rugged and reliable performance and fast switching. They
can be used, with a minimum of effort, in most applications
requiring up to 0.17A DC and can deliver pulsed currents up
to 0.68A. This product is particularly suited to low voltage
applications requiring a low current high side switch.
Features
BSS84: -0.13A, -50V. R_DS(ON) = 10Ω @ V_GS = -5V.
BSS110: -0.17A, -50V. R_DS(ON) = 10Ω @ V_GS = -10V
Voltage controlled p-channel small signal switch.
High density cell design for low R_DS(ON) .
High saturation current.
____________________________________________________________________________________________
S
G
D
Absolute Maximum Ratings
Symbol Parameter
T_A = 25°C unless otherwise noted
BSS84
V_DSS
V_DGR
V_GSS
I_D
P_D
T_J,T_STG
T_L
Drain-Source Voltage
Drain-Gate Voltage (R_GS < 20 KΩ)
Gate-Source Voltage - Continuous
Drain Current - Continuous @ T_A = 30/35^oC
- Pulsed @ T_A = 25^oC
Maximum Power Dissipation T_A = 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering
purposes, 1/16" from case for 10 seconds
-0.13
-0.52
0.36
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient
350
-50
-50
±20
-55 to 150
300
BSS110
-0.17
-0.68
0.63
200
Units
V
V
V
A
W
°C
°C
°C/W
© 1997 Fairchild Semiconductor Corporation
BSS84 Rev. C1 / BSS110. Rev. A2