AN-9068 Datasheet, PDF (1/11 Pages) Fairchild Semiconductor – Gate Resistor Design Guidelines for SupreMOS MOSFETs

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AN-9068
Gate Resistor Design Guidelines for SupreMOS^® MOSFETs
Summary
The faster switching of power MOSFETs enables higher
power conversion efficiency. However, parasitic
components in the devices and boards are involving
switching characteristics more as the switching speed
increases. This creates unwanted side effects, like voltage
spikes or poor EMI performance. To achieve balance, it is
important to have optimized gate drive circuitry because a
power MOSFET is a gate-controlled device. One of critical
control parameters in gate-drive design is external series
gate resistor (R_g). This note suggests minimum and
maximum values of R_g for the SupreMOS^® MOSFETs in
hard-switching applications. As too small R_g results in
excessive dv/dt across drain and source of the MOSFET
during switching-off, low limit is a value that makes
switching dv/dt within the specification in the datasheets.
Silicon Carbide (SiC) Schottky barrier diode, Deuxpeed^®
rectifier, and STEALTH™2 diodes are used for clamp diode
since the diode characteristics affect the dv/dt. Too large R_g
causes loss and poor efficiency; therefore, the upper limit is
chosen to have the same switching losses as the SuperFET^®
MOSFETs or competitors.
Minimum Values According to dv/dt
Table 1 shows low limits of R_g. The unit of R_g in Table 1 is
Ohm (). Since the dv/dt varies by drain current level, it is
tested with two conditions. For example, when using
FCP76N60N with a SiC diode under half of rated current, at
least 13 or larger R_g is required to keep the switching
dv/dt under 50V/ns during switching-off transient.
The dv/dt with a SiC diode is lower than dv/dt with other
diodes due to the bigger junction capacitance of SiC SBD.
A gap of the dv/dt values is getting larger at lower drain
current level and smaller R_g. This is because, at lower
current, the dv/dt is relatively low and the effect of output
capacitance of the MOSFET and diode junction capacitance
on the dv/dt becomes more significant.
If a specific R_g value is needed for other dv/dt not shown in
Table 1, it can be selected by referring to Figure 13 through
Figure 18.
Table 1. Minimum R_g Guidelines Ohms
R_g at 1/2 of I_d
FCP9N60N
FCP11N60N
FCP13N60N
FCP16N60N
FCP22N60N
FCP25N60N
FCA36N60N
FCA47N60N
FCA76N60N
R_g at Rated I_d
FCP9N60N
FCP11N60N
FCP13N60N
FCP16N60N
FCP22N60N
FCP25N60N
FCA36N60N
FCA47N60N
FCA76N60N
dv/dt<100V/ns
SiC Dx S2
0
0
0
0
0
0
0
0
0
0
0 6.8
0
13 18
0
13 18
6.8 13 16
6.8 11 13
6.8 6.8 6.8
dv/dt<100V/ns
SiC Dx S2
6.8 13 18
6.8 13 18
10 16 22
10 13 18
10 16 22
13 16 18
13 16 18
11 13 13
6.8 6.8 10
dv/dt<50V/ns
SiC Dx S2
0
33 36
0
33 36
27 36 39
27 33 36
27 36 39
22 36 36
22 33 36
22 27 27
13 16 16
dv/dt<50V/ns
SiC Dx S2
27 43 47
27 36 39
30 43 47
27 36 39
30 43 47
27 39 43
22 36 39
16 27 27
13 18 18
Upper Limits Considering Switching
Losses
When the SuperFET® MOSFET or other previous-
generation power MOSFET is directly replaced with the
SupreMOS MOSFET, switching losses are reduced, but the
dv/dt may be higher. To control the dv/dt of SupreMOS
MOSFETs, increased R_g is required. In this case, there
should be a limit line for increasing the R_g or switching
losses with SupreMOS MOSFET could be larger. Figure 19
through Figure 54 show switching losses according to R_g for
each device. R_g for similar or less switching loss can be
raised. For example, if 10 is used for a FCA35N60
SuperFET MOSFET, 33 achieves similar E_ON and E_OFF in
under conditions of half of rated drain current and
STEALTH™2 diode.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 4/6/11
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