AN-9048 Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – 6x6 DriverMOS Packaging

AN-9048
Assembly Guidelines for Fairchild’s 6x6 DriverMOS Packaging
By Dennis Lang
INTRODUCTION
The Fairchild 6x6 DriverMOS package is based on
Molded Leadless Packaging (MLP) technology.
This technology has been increasingly used in
packaging for power related products due to its
low package height, excellent thermal performance
with large thermal pads in the center of the
package which solder directly to the printed wiring
board (PWB) and allow modularity in package
design, single and multi-die packages are within the
capability of MLP technology.
The 6x6 DriverMOS has three large die attach
pads allowing direct soldering to the PWB for best
thermal and electrical performance.
These three pads are the high and low side
MOSFETs and the driver. The 6x6 DriverMOS is
designed to be used in high current synchronous
buck DC-DC circuits, saving board space and
component count by integrating several functions
into one package.
This application note focuses on the soldering and
back end processing of the 6x6 DriverMOS.
Circuit design considerations will be addressed in
another application note.
BOARD MOUNTING
The solder joint and pad design are the most
important factors in creating a reliable assembly.
The pad must be designed to the proper
dimensions to allow for tolerances in PWB
fabrication and pick and place, and also to allow
for proper solder fillet formation where applicable.
MLP packages, when the pre-plated lead-frame is
sawn, show bare copper on the end of the exposed
side leads. This is normal, and is addressed by IPC
JEDEC J-STD-001C “Bottom Only Termination”.
However, it has been found that optimized PWB
pad design and a robust solder process will
typically yield solder fillets to the ends of the lead
due to the cleaning action of the flux in the solder
paste.
Figure 1: Bottom side view showing pads for 6x6
DriverMOS
PWB DESIGN CONSIDERATIONS
Any land pad pattern must take into account the
various tolerances involved in production of the
PWB and the assembly operations required for
soldering the DrMOS to the PWB. These factors
have already been taken into consideration on the