AN-9040 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – Power33 Packaging

AN-9040
Assembly Guidelines for Power33 Packaging
By Dennis Lang
INTRODUCTION
The Fairchild Power33 uses a flat leaded package
to achieve SO-8 type performance in a form factor
that is 70% smaller. This packaging technology
has been increasingly used for power related
products due to its low package height, and
excellent thermal performance for size. This is
largely due to the large thermal pad in the center of
the package which solder directly to the printed
wiring board (PWB) and allows a more direct
thermal and electrical path from the drain terminal
out of the package.
BOARD MOUNTING
The solder joint and pad design are the most
important factors in creating a reliable assembly.
The pad must be designed to the proper
dimensions to allow for tolerances in PWB
fabrication and pick and place, and also to allow
for proper solder fillet formation where applicable.
MLP packages, when the pre-plated lead-frame is
sawn, show bare copper on the end of the exposed
side leads. This is normal, and is addressed by IPC
JEDEC J-STD-001C “Bottom Only Termination”.
However, it has been found that optimized PWB
pad design and a robust solder process will
typically yield solder fillets to the ends of the lead
due to the cleaning action of the flux in the solder
paste.
Figure 1: Bottom side view showing pads for
Power33
This application note focuses on the soldering and
back end processing of the Power33.
Figure 2: Solder wetted to lead-frame copper
exposed by singulation on lead ends.