AN-817 Datasheet, PDF (1/10 Pages) Fairchild Semiconductor – Taking Advantage of ECL Minimum-Skew Clock Drivers

AN-817
Fairchild Semiconductor
Application Note
April 1992
Revised May 2000
Taking Advantage of ECL Minimum-Skew Clock Drivers
CLOCK DISTRIBUTION BACKGROUND
Digital systems have tended from their inception toward
incorporation of higher speed elements rather than archi-
tectural changes as the solution to the computational
speed problem. One result of this has been mounting pres-
sure on the semiconductor elements of these systems for
higher speed and all that this implies. Not only the operat-
ing frequency and signal propagation delay but also the rel-
ative timing relationships of devices performing parallel
tasks were challenged. As semiconductor process
improvements pushed operating speeds higher, the evolu-
tion from individually-packaged to multiply-packaged gates
helped reduce delay and speed differences among like
devices. Even so, areas still existed where system design-
ers demanded ever greater improvements in performance
uniformity of digital logic elements. The synchronization
signal generation system, often referred to as the clock
system, is one area in need of such improvement.
Most digital logic systems employ some means of synchro-
nizing the actions carried out by the system’s elements.
The precision with which these various elements are regu-
lated can be shown to have a direct effect on the overall
speed of the system. The less time variation that must be
allocated to the logic elements in the signal path, the faster
that operation may be executed. Therefore, the overall time
to perform all operations may be reduced or the system
speed may be increased. In addition, the coordinated tim-
ing of the synchronizing system itself must benefit from an
equivalent reduction in relative timing of its elements, or
else only limited overall benefit to system performance is
possible.
CLOCK NETWORK ELEMENTS
The typical synchronizing or clock system consists of sev-
eral closely related elements:
• a primary signal source, usually a precisely regulated,
high frequency oscillator,
• frequency dividers to derive lower frequencies from the
primary source,
• distribution amplifiers to boost signal power or supply
separated loads,
• signal delay, duty-cycle alteration or re-synchronizing
elements,
• interconnect wiring, connectors and signal distribution
network,
• and a power source and distribution system for the semi-
conductor devices in the system.
Each of these elements contributes a degree of variability
to the overall timing precision capability of the system. By
virtue of the fact that the physical properties of each ele-
ment can be controlled only within certain limits, the com-
plete system will exhibit a variability somewhat larger than
its elements taken individually. The effect of the variations
contributed by the elements to the overall system variability
is a physical fact that may be demonstrated mathemati-
cally.
Among the factors affecting variability are:
• physical size such as the length of wiring,
• electrical properties such as resistance and charge,
• internally generated and externally induced noise,
• and environmental factors like temperature and altitude.
The visible effect of variability on the system timing is pop-
ularly termed “skew”. Similarly, the individual variabilities of
each element are likewise termed “skew”. The term “skew”
is used also to describe the difference in delay between
like paths taken by signals in a logic device or system.
However, as with many useful terms when carelessly
applied, the term “skew” can lead to some confusion unless
it is more precisely defined.
When applied to the differences in propagation of electrical
signals through like paths in a logic system, the term
“skew” will be taken to mean “differential timing error”. In
terms of the overall effect on the desired timing perfor-
mance of the affected system or device, “skew” will be
defined as “a deviation or asymmetry from the mean or
desired timing value”. The latter meaning of skew will
assume greater importance in the prediction and analysis
of system timing errors to be covered later in this note.
MEETING THE SKEW CHALLENGE
Control of skew in systems is at best a difficult challenge
for design engineers. At its worst, skew can be the thing
that makes or breaks a design. So, to give engineers an
advantage in controlling skew, Fairchild offers ECL devices
specifically designed to minimize the device-related com-
ponent of skew. In addition, the skew properties of these
devices are specified and tested. This has been done to
reduce the design effort required to compensate for device-
related skew effects. The results are tighter system timing
margins, more reliable operation and faster operating
speeds. This means greater system through-put and infor-
mation processing efficiency.
300-SERIES ECL—The Best Weapon Against Skew
300-Series ECL has some natural advantages in the war
on skew. ECL differential amplifiers are minimum-skew by
their very circuit configuration. The fundamental property of
the differential amplifier used as a logic element is bal-
anced switching. The amplifier, Figure 1, is symmetrical.
This results in identical switching delays regardless of out-
put. Following stages are added symmetrically, Figure 2,
so that overall balance is maintained internally. 300-Series
devices designed for minimum-skew also employ a unique
die layout to preserve the basic amplifier balance.
Another advantage of 300-Series ECL is its precise, stable
V_BB reference supply with wide operating power supply
range. This reference is compensated for stability from the
effects of changes in temperature or supply voltage. 300-
Series minimum-skew devices operate from −4.2V to −
5.7V supplies as do all other 300-Series logic devices.
Advanced semiconductor processing, design and manu-
facturing result in uniquely low power consumption for this
ECL family.
© 2000 Fairchild Semiconductor Corporation AN010982
www.fairchildsemi.com