AN-780 Datasheet, PDF (1/5 Pages) Fairchild Semiconductor – Operating ECL from a Single Positive Supply

AN-780
Fairchild Semiconductor
Application Note
May 1991
Revised February 2004
Operating ECL from a Single Positive Supply
Introduction
ECL is normally specified for operation with a negative V_EE
power source and a negative V_TT termination supply. This
is the optimum operating configuration for ECL but not the
only one. Operating ECL from a positive V_CC supply is a
practical alternative that is gaining in popularity. Positive
referenced ECL, or PECL as it is referred to, has been
implemented in various mixed signal ASIC for use in the
Video Graphics and Communications fields and is used in
clock distribution as well. New single supply translator
chips are becoming available to facilitate the interface of
PECL logic levels to TTL and back again. Logic designers
who strive for maximum speed in a system, now can easily
replace sections of TTL logic with ECL and operate in
PECL fashion from the common TTL V_CC supply.
Standard Negative Supply ECL Operation
and Why
Figure 1 shows F100K logic elements operating in stan-
dard negative supply ECL configuration. The most positive
potential is the primary voltage reference for ECL opera-
tion. Standard ECL input and output levels are therefore
negative potentials referenced to the stable passive
Ground (0V). The inherent F100K voltage compensation
permits stable input and output levels over a broad range
of V_EE’s; i.e., −4.2 to −5.7 VDC for 300 Series F100K. Thus
ECL logic operating from a −4.2V V_EE is compatible to logic
operating from a −5.7V supply assuming both are refer-
enced to a common 0V Ground.
Since ECL logic outputs only source currents that originate
from the potential applied to its V_CC/V_CCA pins, the use of a
0V low impedance and low inductance ground potential is
the optimum choice for operation. The use of a continuous
copper ground plane as the primary ECL reference is the
ideal source for the high frequency transient currents
demanded by the logic during switching. Note that despite
the ideal nature of a ground plane as the primary ECL ref-
erence, when mixing TTL (or other noisy circuitry) into ECL
systems, the recommendation is to reference the TTL to a
separate ground plane. This is to keep the high transient
TTL switching energy out of the primary ECL reference and
preserve ECL noise margins.
When F100K ECL output signal interconnection lengths
are direct and short enough, transmission line effects may
be ignored and then only a RE output biasing resistor is
required for logic operation. Please refer to section seven
of the “F100K ECL Logic Databook and Design Guide” for
a more detailed explanation of transmission line effects
and ECL termination techniques. The RE resistor provides
bias to keep the ECL emitter follower output transistor on
for both high and low logic states. The RE resistor is nor-
mally connected between the ECL output and the most
negative potential (V_EE) thus permitting “single” supply
operation.
The V_EE potential will ideally be distributed to the ECL logic
from a power plane or bus which has low DC series resis-
tance and low AC impedance. The low AC impedance is
essential to supply the transient energy needed during
switching. Although the inherent nature of ECL by design is
to maintain essentially constant I_EE current even during
switching, the charging and discharging of internal and
external capacitances and the switching currents in the RE
resistors place transient demands on V_EE. The degree to
which the user can maintain complementary balance of
ECL output loading will greatly influence the nature of the
transient I_EE demands.
F100K 300 Series Voltage Levels Specified for
Standard Negative V_EE Supply Operation
Level
V_OH
V_IH
V_BB
V_IL
V_OL
Min
−1.025
−1.165
−1.83
−1.83
Typ
−0.955
−1.320
−1.705
Max
−0.87
−0.87
−1.475
−1.62
Units
VDC
VDC
VDC
VDC
VDC
Conditions: V_CC/V_CCA = 0.0 VDC Ground
V_EE = −4.2 to −5.7 VDC
RT = 50Ω; V_TT = −2.0 VDC
All Levels W.R.T. Ground
FIGURE 1. ECL Standard Operation from
a Negative V_EE Supply
© 2004 Fairchild Semiconductor Corporation AN010919
www.fairchildsemi.com