AN-7514 Datasheet, PDF (1/4 Pages) Fairchild Semiconductor – Single-Pulse Unclamped Inductive Switching

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AN-7514
Single-Pulse Unclamped Inductive Switching:
A Rating System
Summary
Unexpected transients in electrical circuits are a fact of life.
The most potentially damaging transients enter a circuit on
the power source lines feeding the circuit. Power control and
conversion circuits are vulnerable because of their close
proximity to the incoming lines. The circuit designer must
provide protection or face frequent field failures. Fairchild
offers power MOSFET devices that are avalanche-failure
resistant. Some semiconductor devices are intolerant of
voltage transients in excess of their breakdown rating.
Avalanche-capable devices are designed to be robust. The
Fairchild PowerTrench^® product line typifies rugged power
devices. To assist the designer in their use, Fairchild has
devised an application-specific rating. This application note
is intended to explain and illustrate the use of the single-
pulse Unclamped Inductive Switching (UIS) rating curves.
Failure Mechanisms
Early power MOSFET devices, not designed to be rugged,
failed when the parasitic bipolar transistor indigenous to the
vertical DMOS process turned on. Figure 1 is a cross-section
of a unit cell from an N-channel enhancement mode device.
When a unit is in avalanche, the bipolar transistor is in a
V_CER mode and heats rapidly. The avalanche-induced base-
emitter voltage rises because of a positive resistive
temperature coefficient. Simultaneously, the base emitter
voltage, where the transistor becomes forward biased,
decreases because of its negative temperature coefficient. If
a forward-bias condition is reached, device failure occurs.
Blackburn’s^[1] measurements showed that this failure mode
is a function of avalanche current and junction temperature;
it is not energy related.
Ruggedness improvement technology has advanced to such
a level that devices fail via a different mechanism. Devices
are being designed and manufactured in which the parasitic
bipolar turn-on is effectively suppressed. Device failure is
thermally induced and current is distributed uniformly
across the die. In this case, the failure occurs because the
device junction temperature reaches the point at which the
thermally generated carrier concentration (in the n- region)
becomes comparable to the background doping (also in the
n- region). At this point, the effective charge (sum of the
fixed charge from the doping concentration plus the
thermally generated carriers) in the epi layer becomes too
large to support the applied voltage.
Fairchild PowerTrench^® MOSFET families epitomizes
devices having UIS robustness. UIS capability testing of
these devices shows that the failure current versus the time
in avalanche closely approximates a negative one-half slope
when the locus of device destruction point is plotted on a
log-log graph. Device failure is not inversely proportional to
current only, as it would be in the case of constant energy.
Fairchild supplies rating curves at starting junction
temperatures of 25^°C and 150^°C (see Figure 2).
Figure 1. VDMOS Structure with Parasitic Bipolar Transistor
© 2002 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 10/8/10
www.fairchildsemi.com