AN-7510 Datasheet, PDF (1/13 Pages) Fairchild Semiconductor – A New PSPICE Subcircuit

A New PSPICE Subcircuit for the Power MOSFET
Featuring Global Temperature Options
October 1999
AN-7510
/Title
AN75
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Sub-
ect (A
ew
spice
ubcir-
uit
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OS-
ET
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ng
lobal
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Autho
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Key-
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Inter-
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DOC
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Abstract
An empirical sub-circuit was implemented in PSPICE® and
is presented. It accurately portrays the vertical DMOS power
MOSFET electrical and for the first time, thermal responses.
Excellent agreement is demonstrated between measured
and modeled responses including first and third quadrant
MOSFET and gate charge behavior, body diode effects,
breakdown voltage at high and low currents, gate equivalent
series resistance, and package inductances for
temperatures between -55^oC and 175^oC. Parameter extrac-
tion is relatively straight forward as described.
Introduction
Circuit simulation commonly uses one of the SPICE [1]
programs. However, power circuits require proper models for
unique devices which are not included in the supplied librar-
ies. Efforts have been published to model the power MOS-
FET [2-10] with varying degrees of success. The more
successful papers have used sub-circuit representation. To
date, a thermal model has not been offered.
Objective
It is the goal of this effort to provide for the first time a
thermal sub-circuit model capable of providing accurate sim-
ulation throughout all of the power MOSFET regimes. In
addition the sub-circuit should be readily understood and
accepted by users, and the ease of parameter extraction
should be demonstrated.
Method
A sub-circuit approach is employed which is empirical. It is
developed to provide black box conformity to the power
MOSFET throughout the operating regime normally
traversed by the dictates of most power circuit applications
including junction temperature. Although device thermal
behavior is the driving force, respect is maintained toward
the physics and the SPICE algorithms.
The developed sub-circuit schematic is shown in Figure 1.
There are many forms of SPICE, each with its own strengths
and weaknesses. PSPICE was chosen for the following
reasons.
1. An evaluation copy capable of considerable circuit analy-
sis for power circuits is available.
2. The PROBE feature provides excellent displays.
3. Programmed time slice defaults and DC convergence
routines make it very friendly.
4. The switch algorithm of PSPICE provides a very smooth
transition from off to on.
Other forms of SPICE were not investigated, but they should
be amenable to the development of a similar sub-circuit by
paralleling the teachings of this work.
GATE
1 _LGATE
10
5
DRAIN
-
E_SG 6/8
+
E_VTO
R_{GATE +}
-
18/8
9
20
D_PLCAP
-
V_TO
+
16
6
R_DRAIN
21
MOS1
D_BREAK
MOS2
11 +
E_{BREAK 17/18}
L_DRAIN ²
D_BODY
R_IN
C_IN
-
8
R_SOURCE
L_{SOURCE 3}
7
SOURCE
S1A
12
13/8
S2A
15
14/13
C_A
S1B ¹³
+
S2B
C_B
+ 14
E_{GS 6/8}
E_{DS 5/8}
-
-
R_BREAK
17
I_T
18
R_VTO
19
-
V_BAT
+
FIGURE 1. PSPICE MODEL SUBCIRCUIT
©2002 Fairchild Semiconductor Corporation
Application Note 7510 Rev. A1