AN-7506 Datasheet, PDF (1/9 Pages) Fairchild Semiconductor – Spicing-Up Spice II Software For Power MOSFET

Spicing-Up Spice II Software For Power MOSFET
Modeling
Application Note
February 1994
AN-7506
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The SPICE II simulation software package is familiar to most
designers working in computer-aided design of integrated
circuits. Developed by L. W. Nagel in 1973, SPICE II has
become a widely available, well-understood design tool for
lC modeling and analysis. But, SPICE II has a shortcoming:
its standard simulation programs were developed when all
MOSFETs were low-power devices. Power MOS devices are
growing in use today, both as discrete components and,
potentially, as output stages of power integrated circuits.
SPICE II in its current form doesn’t recognize these new
developments. Its built-in FET models aren’t able to simulate
all the modes of new power MOS device operation. For
example, SPICE II doesn’t recognize the way a power
MOSFET’s internal capacitances change with bias
conditions, the presence of a cascode JFET that compli-
cates both static and dynamic operation, or the presence of
a parasitic body diode that affects operation in the third
quadrant. Without this information, SPICE II will predict
power MOSFET performance that is incorrect.
Since SPICE II’s internal device models can’t be easily
changed for all existing copies, we looked for another
approach to update the capabilities of this widely used simu-
lation package in its standard form. Adding a “subcircuit” of
external components that complement the devices within the
SPICE II software, so as to form a true, equivalent circuit of a
power MOSFET, is the answer.
The subcircuit works nicely with the standard SPICE II
software, providing a model with all the terminal characteris-
tics of a power MOSFET. Parameters of the subcircuit model
can be determined from simple terminal measurements or
from standard data sheets, using the algorithmic and empiri-
cal approach described below. Once these parameters are
in place, SPICE II can be used to accurately simulate either
p-channel or n-channel power MOSFET devices over a wide
range of currents and voltages. The subcircuit functions as
an embedded subroutine, so it can be used repetitively for
any number of power MOSFETs in a design. This technique
can be used to model power MOSFETs with any version of
the SPICE II program presently available, without any modifi-
cations to its internal source code. The technique can also
be used with other commercially available or in-house-devel-
oped circuit simulators.
Page-
ode
Use-
Modeling The Power MOSFET
A cross-sectional view of a cell of a Fairchild IRF130 power
MOSFET is shown in Figure 1. The easiest way to understand
its electrical characteristics is to think of it as a vertical JFET,
driven in cascode from a low-voltage lateral MOSFET.^{1, 2}
When the gate is positively biased with respect to the n-bulk,
an accumulation layer forms in the n-region beneath the gate.
This layer acts as the drain of the lateral MOSFET, as well as
the source of the vertical JFET. The JFET channel is then-
region between the two p-type body diffusions, which act as
the gate of the JFET. The JFET drain is the n+ bulk, usually
thought of as the power MOSFET drain.
+n SOURCE
SOURCE METAL
POLY GATE SiO₂ GATE OXIDE
p+
MOS
JFET
0V
p BODY
10V
DEPLETION _40V
LAYER
n+ DRAIN
FIGURE 1. A CROSS-SECTIONAL VIEW SHOWS THE PHYSI-
CAL MAKEUP OF THE LATERAL LOW-VOLTAGE
MOSFET AND VERTICAL JFET THAT OPERATE IN
CASCODE AS THE POWER MOSFET.
When you look at the power MOSFET this way, it becomes
possible to use the standard SPICE II built-in device models,
because SPICE II can simulate both the vertical JFET and
the lateral MOSFET. When we use the subcircuit to add the
rest of the Fairchild IRF130 power MOSFET to these SPICE
II-simulated devices, we get a satisfactory equivalent circuit,
shown in Figure 2.
The gate-to-source capacitance of the Fairchild IRF130
power MOSFET is represented by C₂₁. It is really a compos-
ite of two capacitances. The first is formed between the poly-
silicon gate and source metal (with the thick oxide as a
dielectric). The second is formed between the gate and the
n+ source (with the thin oxide acting as the dielectric). The
value of C₂₁ is essentially unchanged by voltage or current.
Capacitor C₂₄ is formed between the power MOSFET gate
and the accumulation layer, with the thin gate oxide as a
dielectric. So long as the gate is positive with respect to the
n-neck region, the accumulation layer exists and C₂₄ doesn’t
change. But, if the external drain voltage (less their voltage
drop across then-drift region) approaches the gate voltage,
the accumulation layer starts to disappear. When that
happens, C₂₄ abruptly drops in value. This sudden change
has to be taken into consideration.
©2002 Fairchild Semiconductor Corporation
Application Note 7506 Rev. A1