AN-7018 Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Segmented Voltage Regulator Modules

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AN-7018
Segmented Voltage Regulator Modules (VRM) as a
Solution for CPU Core Voltage
Alan Elbanhawy, Fairchild Semiconductor
Abstract
The PC industry continues to move closer to the goal of
having DC/DC converters that deliver up to 150–200 Amp at
0.95V in the near future. This goal may be an achievable one
if engineers carefully consider all of the loss mechanisms,
especially loss mechanisms are that most pronounced at high
currents such as 30A to 40A per phase. As a step in moving
closer to this goal, we have developed a segmented VRM in
the form of several modules with each one being capable of
delivering up to 40 Amps per phase at efficiency over 80%.
With a five phase design, DC/DC converters could deliver
200 Amps. This approach divides a multi-phase DC-DC
converter into the following sections:
1. PWM controller and its associated components.
2. Power MOSFETs, MOSFET driver, Output inductor
and associated components.
3. Input and output capacitors bank comprising ceramic
and electrolytic type.
This application note will address only point (2) above i.e.,
the power train. The selection of the controller and the output
and input capacitors is fairly standard and may be found in
the technical publications. For each phase, the components
on point (2) above which constitute all the power
components are placed on a small plug-in board of 1.15" x
0.85" that delivers 40 Amps and receives the PWM TTL
signal from the controller. This module has a footprint of
about 0.85" x 0.25" of the motherboard space and may be
placed anywhere on the board as close as possible to the
CPU reducing the transmission impedance and losses and
giving the Motherboard designer the flexibility to optimize
the power and PCB space utilization. Each modular board
may be fitted individually with its own heat sink.
Design Approach
By examining the loss mechanisms in a synchronous buck
converter the individual impact on the module efficiency can
be assessed and will allow us to address different choices to
be made in component selection and PCB layout techniques.
Loss mechanisms may be grouped as follows:
• Conduction losses = Iload^2*RDS(on)*Duty Cycle. Since
both the maximum current, Iload is determined by the
application and the Duty Cycle is determined by the input
and output voltages specs, we only have RDS(on) to
minimize for the lowest possible losses. In a synchronous
buck converter operating from 12-volt input and
generating an output voltage of 1 Volt, the duty cycle for
the synchronous rectifier is about 91.7% this leads us to
select the MOSFET with the lowest available RDS(on).
By reviewing available MOSFETs datasheets, it is clear
that one device will not have a low enough RDS(on) to
achieve acceptable losses and hence we have to select two
to do the job. The conduction losses for the high side
MOSFET is much lower with a duty cycle of 8.3%, which
means that we can tolerate a higher RDS(on). But as we
will see in the next point a balance must be struck
between the on-resistance, RDS(on) and the miller charge,
Qgd and the post gate threshold gate-source charge, Qgsp
to minimize the total losses. This is addressed in the next
point.
• Dynamic losses = 0.5*(Rise Time + Fall Time)* Input
Voltage*Iload*Switching Frequency. This form of losses
is predominant in the high side MOSFET. By closely
examining the above equation we can partition the
individual parameters influence as follows:
• The rise and fall times are dominated by the MOSFET
Qgd and Qgsp. The high side MOSFET must have the
lowest possible Qgd and Qgsp with an acceptable on-
resistance RDS(on) to satisfy the previous point. At 40
Amps output current the conduction losses still dominate
dictating the choice of the most suitable device to have as
low as possible RDS(on) even at the expense of higher
dynamic losses to achieve the optimum combined
dynamic and conduction losses. This very fact, lead us to
select a MOSFET typically used for the synchronous
rectifier application for the high side device to minimize
the total losses.
• The rise and fall times are also dependant on the gate
driver source resistance, rise and fall time of the drive
waveforms and maximum source and sink currents.
Pspice testing done in preparation for this work shows
clearly that we ideally need a driver that is capable of
delivering 4–5 Amps and a drive signal of about 3–5ns
rise and fall times. Unfortunately such drivers are not
available in the market right now instead, we selected a
driver capable of delivering 2 amps at rise and fall times
of slightly over 5 ns.
• The switching frequency is sometimes determined based
on the control loop bandwidth requirements, maximum
REV. A 9/30/05