AN-684 Datasheet, PDF (1/7 Pages) Fairchild Semiconductor – 100336 Four-Stage Counter/Shift Register

AN-684
Fairchild Semiconductor
Application Note
February 1990
Revised May 2000
100336 Four-Stage Counter/Shift Register
INTRODUCTION
Many system designs require bi-directional counting and
shifting functions. In most cases these functions are sepa-
rate and unique requirements within the system design.
For this reason, separate catalog parts are available. In
some cases however, there is a requirement to have a
device that will allow both counting and shifting functions.
This is especially true in arithmetic, timing, sequential, or
communication applications. Fairchild offers a very versa-
tile counter/shift register in the 100336. This application
note describes its function in detail and offers some simple
uses.
DESCRIPTION
The 100336 contains four synchronous, presettable flip-
flops. Synchronous operation is provided by having all flip-
flops clocked simultaneously so that all output changes
coincide. This mode of operation eliminates counting
spikes on the outputs which are normally associated with
asynchronous counters. The clock input is buffered and
triggers the four flip-flops on the rising (positive-going)
edge.
The counters are fully programmable allowing the outputs
to be set to either a HIGH (1) or LOW (0). As presetting is
synchronous, setting low levels on the select inputs (S₀-S₂)
(see Table 1) disables the counter and causes the outputs
to agree with the parallel inputs (P₃–P₀) on the next rising
edge of the clock. Loading is accomplished regardless of
the levels of the two enables (CEP, CET).
TABLE 1. Function Select Table
S₂
S₁
S₀
Function
L
L
L
Parallel Load
L
L
H
Complement
L
H
L
Shift Left
L
H
H
Shift Right
H
L
L
Count Down
H
L
H
Clear
H
H
L
Count Up
H
H
H
Hold
The 100336 features both synchronous and asynchronous
clear functions. The synchronous clear is performed by set-
ting a binary five (101B) at the select inputs. On the next
rising edge of the clock, the outputs will be forced LOW
(0000) regardless of the levels at the enable inputs. A buff-
ered asynchronous master reset (MR) is provided to clear
all outputs LOW (0000) regardless of the levels of the
clock, select, or enable inputs.
Count up/count down functions are selected with the select
inputs (S₂–S₀). These are synchronous operations and the
outputs will increment/decrement in value on the rising
edge of the clock. Both count enable inputs (CEP, CET)
must be true (LOW) to count. The terminal count output
(TC) becomes active-LOW when the count reaches zero in
the DOWN mode or fifteen in the UP mode. Its duration is
approximately equal to one period of the clock. The TC out-
put is not recommended for use as a clock or synchronous
reset for flip-flops. See Figure 1 for timing relationships in
UP/DOWN counting.
In simple ripple-carry cascading applications the terminal
count TC is fed forward to enable the trickle enable (CET)
input. This method is increasingly inefficient as the count-
ing chain lengthens. The upper limit of the clock frequency
is determined by the clock-to-terminal-count delay of the
first stage, the cumulative trickle-enable (CET)-to-terminal-
count delay of the intermediate stages, and the trickle-
enable-to-clock delay of the last stage. For faster counting
rates a carry-lookahead scheme is necessary. In this
scheme the ripple delay through the intermediate stages
commences with the same clock that causes the first stage
to change over from MAX to MIN in the UP mode, or from
MIN to MAX in the DOWN mode. Since the final count
cycle takes 16 clocks to complete, there is ample time for
the ripple to propagate through the intermediate stages.
The critical timing that limits the counting rate is the clock-
to-terminal-count of the first stage plus the parallel-enable-
to-clock (CEP) setup time of the last stage. Figure 2 shows
the connections for the fast-carry counting scheme.
© 2000 Fairchild Semiconductor Corporation AN010646
www.fairchildsemi.com