AN-683 Datasheet, PDF (1/2 Pages) Fairchild Semiconductor – 300 MHz Dual Eight-Way Multiplexer/Demultiplexer

AN-683
Fairchild Semiconductor
Application Note
January 1990
Revised May 2000
300 MHz Dual Eight-Way Multiplexer/Demultiplexer
INTRODUCTION
High speed multiplexing and demultiplexing is an integral
part of the fast expanding telecommunications market, and
can be used successfully in inter-computer and intra-com-
puter wide-path communications. The Fairchild family of
F100K ECL components provides an excellent solution to
this design problem. This applications note describes a
data transmission scheme that can transfer information at
the rate of 75 Mbytes per second using only four twisted
pair transmission lines.
Using 100341 8-Bit Shift Registers as parallel to serial and
serial to parallel converters it is possible to design a simple
mux/demux that can operate at speeds as high as 300
MHz (Figure 1). The data to be multiplexed onto the trans-
mission lines are applied as 16 bits (2 bytes) in parallel to
the inputs of the 100341s where they are loaded into the
registers under control of a synchronization pulse (SYNC).
The mode of the 100341s is then changed to shift right and
the data is transmitted on the output lines at the clock rate.
When the last bit has been shifted out, the register is
loaded with the next data to be transmitted.
FIGURE 1. 300 MHz Dual Eight-Way Multiplexer/Demultiplexer
The clock signal (CLOCK) is a free-running 300 MHz
square wave and the synchronization signal (SYNC) goes
low for one clock cycle in every eight. These two signals
are transmitted along with the data to facilitate synchro-
nized reception at the other end.
At the receiving end, the 100341s are used as simple shift
registers that accomplish the task of demultiplexing the
data. The SYNC signal controls the loading of the 100351
receiver registers.
© 2000 Fairchild Semiconductor Corporation AN010645
www.fairchildsemi.com