AN-6741 Datasheet, PDF (1/8 Pages) Fairchild Semiconductor – Flyback Power Supply Control

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AN-6741
Flyback Power Supply Control with the SG6741
Summary
This application note describes a design strategy for a high-
efficiency, compact flyback converter. Design
considerations, mathematical equations, and guidelines for a
printed circuit board layout are presented.
Features
ƒ High-voltage startup
ƒ Low operating current: 4mA
ƒ Linearly decreasing PWM frequency to 22KHz
ƒ Frequency hopping to reduce EMI emission
ƒ Peak-current-mode control
ƒ Cycle-by-cycle current limiting
ƒ Leading-edge blanking
ƒ Synchronized slope compensation
ƒ Gate output maximum voltage clamp: 18V
ƒ V_DD over-voltage protection (OVP)
ƒ V_DD under-voltage lockout (UVLO)
ƒ Internal open-loop protection
ƒ Constant power limit (full AC input range)
Description
The highly integrated SG6741 series of PWM controllers
provides several features to enhance the performance of
flyback converters.
To minimize standby power consumption, a proprietary
green mode provides off-time modulation to linearly
decrease the switching frequency at light-load conditions.
To avoid acoustic-noise problems, the minimum PWM
frequency is set above 22KHz. This green mode enables the
power supply to meet international power conservation
requirements. With the internal high-voltage startup
circuitry, the power loss due to bleeding resistors is also
eliminated. To further reduce power consumption, the
SG6741 is manufactured using BiCMOS process, which
allows an operating current of only 4mA.
The SG6741 integrates an internal frequency hopping
function to reduce the EMI emission of a power supply with
minimal line filtering; while the built-in synchronized slope
compensation maintains a stable peak-current-mode control.
The proprietary internal line compensation ensures constant
output power limit over a wide AC input voltages, from
90V_AC to 264V_AC.
The SG6741 provides many protection functions. In
addition to cycle-by-cycle current limiting, the internal
open-loop protection circuit ensures safety should an open-
loop or output short-circuit failure occur. The PWM output
is disabled until the voltage drops below the UVLO lower
limit, then the controller starts again. As long as V_DD
exceeds about 26V, the internal OVP circuit is triggered.
© 2006 Fairchild Semiconductor Corporation
Rev. 1.2.1 • 10/20/08
www.fairchildsemi.com