AN-6612 Datasheet, PDF (1/2 Pages) Fairchild Semiconductor – A Novel JFET Micro-Power Voltage Regulator

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AN-6612
A Novel JFET Micro-Power Voltage Regulator
Many systems require a stable voltage supply to maintain
constant performance. When these systems are battery-
operated, a regulator is needed to stabilize the system
voltage as the battery decays with time. Unfortunately, IC
voltage regulators require several milliamps of quiescent
current, making them impractical for micro-power
applications. Zener diodes may also be impractical because
of short term peak current requirements of the system. This
could require additional buffering or high standby currents,
but both increase the battery drain. An inexpensive micro-
power voltage regulator is needed to fill the gap between IC
regulators (high quiescent current) and Zener diodes (high
standby current).
Instead of the traditional bipolar approach, the regulator
shown in Figure 1 uses a JFET as the series pass element.
This offers several advantages: first, no pre-regulation is
needed for the pass element as with an NPN bipolar because
the drive comes from the regulated output. Next, the gate-
source is isolated from the line via the drain, thus offering
excellent line regulation. This is not the case with PNP
bipolar pass elements, where the emitter is the input.
Finally, and possibly the most important feature for micro-
power regulators, is JFETs require no current drive.
The emitter-base breakdown voltage of Q3 is used as a
reference (~7.2 V) in conjunction with Q2 to form a shunt
regulator. The shunt current drives a current mirror, Q4-Q5,
which creates the gate drive voltage of the pass JFET. The
value of the shunt current is determined by R3 and the V_GS
of the pass JFET (I_R3 ~ I_SHUNT). High load currents will
reduce the shunt current because the JFET V_GS is lower.
Temperature stability is achieved by cancelling the drift of
Q2 and Q3's V_BE (~-2 mV/°C/transistor) with the BV_EB drift
of Q3 (~3 mV/°C) resulting in a negative drift at the base of
Q2, and the output, of 1 mV/°C.
Selection of the JFET requires some care. Ideally, the JFET
I_DSS needs to be greater than the load current at all
temperatures (I_DSS has a temperature coefficient of
~−0.7%/°C) and the breakdown voltage should be greater
than the maximum input voltage. Practically, the JFET I_DSS
needs to be much larger than the maximum load current.
Linear operation requires the JFET's drain to gate voltage
(V_DG) to be greater than the pinch-off voltage V_P. By
operating the JFET at currents much less than I_DSS, the gate
to source voltage (V_GS) will be close to V_P (V_GS = V_P (1-
(I_D/I_DSS)^1/2)) allowing small drain to source voltages (V_DS).
For linear operation:
Figure 1. Micro-power Regulator
© 2014 Fairchild Semiconductor Corporation
Rev. 1.0 • 7/16/15
It should be noted that N channel JFET's can be paralleled
for higher load current requirements without matching the
devices.
Actual performance of the regulator is quite good. With a
10 V typical output, the line regulation is within ±0.05% for
a range of VIN-VOUT of 0.3 V to 10 V. The load regulation
is 0.2% with a load range of 10 µA to 10 mA (Z_O ~ 10 )
and the temperature stability is −0.01%/°C (~1 mV/°C). The
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