AN-6300 Datasheet, PDF (1/13 Pages) Fairchild Semiconductor – Highly Integrated Quasi-Resonant PWM Controller

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AN-6300
FAN6300 / FAN6300A / FAN6300H
Highly Integrated Quasi-Resonant PWM Controller
Abstract
This application note describes a detailed design strategy for
higher-power conversion efficiency and better EMI using a
Quasi-Resonant PWM controller compared to the
conventional, hard-switched converter with a fixed
switching frequency. Based on the proposed design
guideline, a design example with detailed parameters
demonstrates the performance of the controller.
Introduction
The highly integrated FAN6300/A/H PWM controller
provides several features to enhance the performance of
flyback converters. FAN6300/A are applied on Quasi-
Resonant flyback converter where maximum operating
frequency is below 100kHz and FAN6300H is suitable for
high frequency operation that is around 190kHz. A built-in
High Voltage (HV) startup circuit can provide more startup
current to reduce the startup time of the controller. Once the
VDD voltage exceeds the turn-on threshold voltage, the HV
startup function is disabled immediately to reduce power
consumption. An internal valley voltage detector ensures
power system operates in quasi-resonant operation in wide-
range line voltage and reduces switching loss to minimize
switching voltage on drain of the power MOSFET.
To minimize standby power consumption and improve light-
load efficiency, a proprietary green-mode function provides
off-time modulation to decrease switching frequency and
perform extended valley voltage switching to keep to a
minimum switching voltage.
FAN6300/A/H controller provides many protection
functions. Pulse-by-pulse current limiting ensures the fixed
peak current limit level, even when short-circuit occurs.
Once an open-circuit failure occurs in the feedback loop, the
internal protection circuit disables PWM output
immediately. As long as V_DD drops below the turn-off
threshold voltage, the controller also disables the PWM
output. The gate output is clamped at 18V to protect the
power MOS from high gate-source voltage conditions. The
minimum t_OFF time limit prevents the system frequency from
being too high. If the DET pin reaches OVP level, internal
OTP is triggered, and the power system enters latch-mode
until AC power is removed.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.2 • 5/21/10
www.fairchildsemi.com