AN-6024 Datasheet, PDF (1/6 Pages) Fairchild Semiconductor – Understanding Analog Video Signal Clamps, Bias, DC-Restore, and AC or DC Coupling Methods

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AN-6024 — FMS6xxx Product Series
Understanding Analog Video Signal Clamps, Bias,
DC-Restore, and AC or DC Coupling Methods
Description
The video filter, driver, and switch matrix products offered
by Fairchild Semiconductor have various input coupling
and clamping configurations. Choices include input AC or
DC coupling, output AC or DC coupling, and various input
clamping and bias configurations. An example would be the
classic sync strip and pulse-DC-restore circuit or,
alternatively, the continuous time clamp/bias circuit. Each
type of coupling/clamping implementation has specific
advantages and disadvantages for a specific application.
Most designs incorporate a single supply running from 5V
down to 2.7V. Designers must be concerned about whether
or not the video signal will be clipped at 2.7V V_CC and
ensure that proper DC biasing is established at the input.
Users of these video products should understand the
specifics of the input and output analog video signal. If the
input is a 140-IRE 1V_pp with 75% saturation CVBS signal,
care must be taken to bias the signal within the input
common mode range of the amplifier. The systems designer
must not forget that the CVBS signal can have 100%
saturation, which increases the input signal amplitude to
1.23V_pp and requires a system design that accommodates
this signal without causing signal clipping.
Analog component video essentially maintains the same
luma (Y) as CVBS, but keeps the color information
separated. Pb is the blue color difference signal and Pr is the
red color difference signal. Component analog video (Y, Pb,
Pr) includes several different formats: standard definition
(SD), enhanced definition (ED or PS), and high definition
(HD). Special attention must be given to setting the optimal
bias conditions of these inputs; whether they are AC or DC
coupled from the driving device.
Figure 1 shows the various video formats with appropriate
signal amplitude and bias levels.
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 7/11/06
www.fairchildsemi.com