AN-5241 Datasheet, PDF (1/5 Pages) Fairchild Semiconductor – Guidelines for Pb-Free Soldering of Fairchild Components Based on JEDEC J-STD 20D / IEC EN 61760-1 2006

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AN-5241
Guidelines for Pb-Free Soldering of Fairchild Components
Based on JEDEC^® J-STD 20D / IEC EN 61760-1:2006
Introduction
The basic concepts behind the Pb-free SMT reflow process
are the same as the old industry standard Sn63Pb37 solder
used for decades in the electronics industry. The proper
characterization of the equipment, with consideration given
to the board component loading, as well as the selection of
the appropriate materials and printing process, result in a
reliable, high-yield, low-rework assembly run. Similarly,
proper characterization of the Pb-free wave-solder process
results in consistent wetting of the terminals and through-
holes with no damage to surface mounted components on
the same board. This application note presents Fairchild’s
recommendation for a starting point for SMT and wave
solder profiles; however, it is critical to recognize that a
soldering profile that works for one board and material set
likely differs from other production runs if the material or
board design is different.
Solder Profile Basics
The placement of the thermocouples is critical for an
accurate solder profile. Industry experts, such as Jabil
Circuit1, recommend a review of the leaded components on
the board to establish the hot spots, such as the package
body, and cold spots, such as the terminal (where it sits on
the land pattern). For array packages, such as WLCSP and
BGA, it is a little more challenging, but very important;
especially with large array packages. The top of the body is
selected and, for the terminals, the recommendation is to
drill a hole in the middle of the center ball and one of the
perimeter balls to insert the thermocouples. Generally,
selection of the largest components is desired for the
thermocouples as they are slowest to reflow due to their
thermal mass. The smallest packages and edges of the
printed circuit board (PCB) should also be considered, as
these heat quickly and could be overstressed if exposed to
extended heating. Fairchild strongly suggests that customers
review recommendations in JEDEC^® JEP140 for
thermocouple use.
Package Peak Temperature
JEDEC^® J-STD 020D recommends that the target peak
package temperature for Moisture Sensitivity Level (MSL)
assessment be selected based on package volume and
thickness. J-STD 020D is “…not meant to specify board
assembly profiles;”^[2] however, to prevent component
damage, actual SMT profiles should not exceed the
parameters J-STD 020D Table 5-2, reproduced below:
Table 1. J-STD 020D Table 5-2
Thickness
(mm)
Volume (mm3)
<350
350-2000
>2000
<1.6
260c
260c
260c
1.6-2.5
260c
250c
245c
>2.5
245c
245c
245c
Note:
1. All Fairchild packages are rated for Pb-free solder using
JEDEC^® J-STD 020D MSL classification specification
solder profile and are backward compatible with
conventional Sn63Pb37 solder. Packages receiving an
MSL rating greater than one may need to be baked
before assembly, depending on storage conditions (see
product packaging for recommendations / requirements).
The Reflow Process^[3]
Refer to Figure 1 for an illustration of a typical Pb-free
Surface Mount (SMT) reflow profile.
In the reflow process, each of the process zones is critical
for good performance.
The preheat zone’s purpose is to evaporate any solvents in
the solder paste or in the construction of the board. A ramp
rate of three degrees centigrade per second (3°C/s) is the
maximum recommendation to avoid splattering, bridging of
solder fillets, slump, or solder-ball creation. Careful control
of the ramp rate also helps avoid thermal shock stress of the
components and the PCB.
© 2013 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 10/8/13
www.fairchildsemi.com