AN-5053 Datasheet, PDF (1/5 Pages) Fairchild Semiconductor – Devices with a Synchronous Pixel Interface

www.fairchildsemi.com
Application Note AN-5053
tm
Devices with a Synchronous Pixel
Interface
Introduction
A synchronous pixel interface format is typically made up of
n-bits of color data, VSYNC and HSYNC frame and line
synchronization signals, and a free-running pixel clock that
runs continuously while the display is being updated. Pixel
interfaces can be RGB, YUV, or other formats. For the
purpose of simplicity, this application note typically refers to
an RGB interface, but the information is equally applicable
to other formats.
Standard 16- and 18-bit RGB display interfaces can be
readily serialized and deserialized through use of the
FIN224AC. For 8- and 10-bit RGB and YUV interfaces, the
FIN212AC would be a more optimal solution. The
FIN224AC has been designed to work synchronously over
an input pixel clock frequency range of 2MHz to 26MHz.
The FIN212AC can operate between 5MHz and 40MHz.
Lower frequencies of operation can be done by over sam-
pling the data or
running in a PLL-bypass mode. Bursting data through the
device is also supported. Each of these methods of transfer-
ring data is explained below. For simplification purposes,
only the FIN224AC is referenced, though the discussion is
applicable to the FIN212AC, with minor differences.
Synchronous RGB Display
Interface with No Frame Buffer
A standard RGB interface sends data synchronously from
the display interface to the actual display. Data runs
continuously with one word of data being sent with each
pixel clock. A standard RGB interface consists of a bank of
data signals used to represent the desired color DATA[0:n], a
vertical synchronization signal (VSYNC), a horizontal syn-
chroni-zation signal (HSYNC), and a pixel clock. From the
FIN224AC serializer perspective, the DATA, VSYNC, and
HSYNC signals are all considered data inputs and all are
treated identically. For a 16-bit data interface, an additional
four-control signals could also be sent across the interface.
When operating in this mode, the LCD interface pixel clock
input is used as both the reference clock (CKREF) input and
the data strobe (STROBE) input. The CKREF signal is used
as the reference signal for the FIN224AC internal PLL. The
STROBE signal is used to latch data into the serializer and
initiate the serialization sequence.
Figure 1 shows a simple schematic representation of a RGB
data interface. Assuming that there are two bits reserved for
vertical synchronization and two bits for horizontal synchroni-
zation and that the display is being refreshed 60 times per sec-
ond, the required input clock rate is 4.675MHz (242x322x60).
Each frame of data requires 16.67ms to be sent.
TP6
PIXCLK_M
GPIO_MODE
LCD_ENABLE_M
LCD_VSYNC_M
LCD_HSYNC_M
LCD17_M
LCD16_M
LCD15_M
LCD14_M
LCD13_M
LCD
LCD12_M
LCD11_M
Controller LCD10_M
Out
LCD9_M
LCD8_M
LCD7_M
LCD6_M
LCD5_M
LCD4_M
LCD3_M
LCD2_M
LCD1_M
LCD0_M
µSerDes Serializer
VDDP ^U20
FIN224AC
A6
B5
CKREF
STROBE
F6
F5 ^DIRI
J6 ^S2
S1
J5
J4
J3
F3
J2
J1
F2
DP24
DP23
DP22
DP21
DP20
DP19
F1 ^DP18
E2 ^DP17
E1 ^DP16
D2
D1
C2
B1
B2
A1
C3
DP15
DP14
DP13
DP12
DP11
DP10
DP9
A2 ^DP8
B3 ^DP7
A3 ^DP6
C4
A4
DP5
DP4
B4
A5
DP3
DP2
DP1
DIRO ^B6
C1
CKP
DSO+/DSI-
DSO-/DSI+
CKSO-
CKSO+
CKSI-
CKSI+
VDDA
VDDS
VDDP
D6
D5
C6
C5
E6
E5
2.8V
F4
1.8V
E4
D3
C6
C3
1nF .01µF
µSerDes DeSerializer
U22
FIN224AC
J6
F5
S2
F6 ^S1
DIRI
B5
A6
STROBE
CKREF
B6 _DIRO
2.8V
2.8V
C12
.01µF
C11 C10
2.2µF 1nF
D5
D6
DSO-/DSI+
DSO+/DSI-
E6
E5
CKSI-
CKSI+
C6
C5 ^CKSO-
CKSO+
F4
E4
VDDA
D3
VDDS
VDDP
C1
CKP
DP24
DP23
DP22
DP21
DP20
DP19
J5
J4
J3
F3
J2
J1
F2
DP18 _F1
DP17 _E2
DP16 _E1
DP15
DP14
DP13
DP12
DP11
DP10
DP9
D2
D1
C2
B1
B2
A1
C3
DP8 _A2
DP7 _B3
DP6 _A3
DP5
DP4
C4
A4
DP3
DP2
DP1
B4
A5
TP5
PIXCLK_S
LCD_ENABLE_S
LCD_VSYNC_S
LCD_HSYNC_S
LCD17_S
LCD16_S
LCD15_S
LCD14_S
LCD13_S
LCD12_S
LCD11_S
LCD10_S
LCD9_S
LCD
LCD8_S
Display
LCD7_S
LCD6_S
In
LCD5_S
LCD4_S
LCD3_S
LCD2_S
LCD1_S
LCD0_S
Assumptions:
1) 18-bit Unidirectional RGB Application
2) Mode 2 Operation (5Mhz to 15Mhz CKREF)
3) VDDP= (1.65V to 3.6V)
Firgure 1.16-Bit RGD LCD Display Interface
Rev. 1.3.4 • 8/22/07